HAOUAS Elyes has uploaded this change for review.
nb/intel/i945: Use macro instead of magic number
Aslo add comments on Read/Write-Once bits.
ULBA register is 64bits, so maybe there is a typo
on RCBA(0x114) and it should be 0x11b insted.
Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M 3rdparty/blobs
M src/northbridge/intel/i945/early_init.c
2 files changed, 8 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
index 16058e5..998982d 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 16058e552279b4884b1f671e7a78752d28abd1cc
+Subproject commit 998982d714a08481bb4944f456929be06b5e696f
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 6bfa1c7..70b8152 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -883,10 +883,13 @@
static void ich7_setup_root_complex_topology(void)
{
- RCBA32(0x104) = 0x00000802;
- RCBA32(0x110) = 0x00000001;
- RCBA32(0x114) = 0x00000000;
- RCBA32(0x118) = 0x00000000;
+ /* FIXME: ESD [23:16] is R/WO */
+ RCBA32(ESD) = 0x00000802;
+ /* FIXME: ULD [31:16] is R/WO */
+ RCBA32(ULD) = 0x00000001;
+ /* FIXME: ULBA [63:0] is R/WO */
+ RCBA32(0x114) = 0x00000000; // RCBA32(0x11b) ?
+ RCBA32(ULBA) = 0x00000000;
}
static void ich7_setup_pci_express(void)
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