Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33035
Change subject: src/soc/intel/common/block/sgx: Add missing new lines ......................................................................
src/soc/intel/common/block/sgx: Add missing new lines
Added missing new lines to Debug Output.
Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/soc/intel/common/block/sgx/sgx.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33035/1
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 2d4cc53..60714d9 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -100,8 +100,8 @@ return; }
- printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64); - printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64); + printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64); + printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64);
/* Program core PRMRR MSRs. * - Set cache writeback mem attrib in PRMRR base MSR
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33035 )
Change subject: src/soc/intel/common/block/sgx: Add missing new lines ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33035 )
Change subject: src/soc/intel/common/block/sgx: Add missing new lines ......................................................................
src/soc/intel/common/block/sgx: Add missing new lines
Added missing new lines to Debug Output.
Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb Signed-off-by: Christian Walter christian.walter@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035 Reviewed-by: Philipp Deppenwiese zaolin.daisuki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/sgx/sgx.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 2d4cc53..60714d9 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -100,8 +100,8 @@ return; }
- printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64); - printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64); + printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64); + printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64);
/* Program core PRMRR MSRs. * - Set cache writeback mem attrib in PRMRR base MSR
-
Christian Walter (Code Review) -
Patrick Georgi (Code Review)
-
Philipp Deppenwiese (Code Review)