Patrick Georgi merged this change.

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Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved
src/soc/intel/common/block/sgx: Add missing new lines

Added missing new lines to Debug Output.

Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/intel/common/block/sgx/sgx.c
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 2d4cc53..60714d9 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -100,8 +100,8 @@
return;
}

- printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64);
- printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64);
+ printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64);
+ printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64);

/* Program core PRMRR MSRs.
* - Set cache writeback mem attrib in PRMRR base MSR

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb
Gerrit-Change-Number: 33035
Gerrit-PatchSet: 2
Gerrit-Owner: Christian Walter <christian.walter@9elements.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged