Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor it out. It does not match the devicetree, so also add a FIXME comment.
Tested with BUILD_TIMELESS=1, Intel RVP7 does not change.
Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 4 files changed, 5 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43908/1
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 898739c..60cbb4e 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -127,7 +127,11 @@ device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index a269d01..355f199 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -10,7 +10,6 @@ register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 07d7385..a0984ea 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -14,7 +14,6 @@ register "gen2_dec" = "0x000c0201"
# FSP Configuration - register "HeciEnabled" = "0" register "PmTimerDisabled" = "1"
# VR Settings Configuration for 4 Domains diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 91abfe6..f15072c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -8,7 +8,6 @@ register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
Patch Set 1: Code-Review+2
Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43908
to look at the new patch set (#2).
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor it out. It does not match the devicetree, so also add a FIXME comment.
Tested with BUILD_TIMELESS=1, all four variants do not change.
Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 4 files changed, 5 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43908/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... File src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... PS4, Line 132: empty line
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... PS4, Line 133: does not match devicetree! HECI is will function disable hence PCI enumeration is required bt setting below HeciEnabled config will ensure device is not visible to PCI tree after booting to OS. But that doesn't mean, HECI is not functional. this is to fix OS HECI driver issue after booting to OS.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... File src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... PS4, Line 133: does not match devicetree!
HECI is will function disable hence PCI enumeration is required bt setting below HeciEnabled config […]
Thanks for the explanation, will remove the FIXME
Hello build bot (Jenkins), Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43908
to look at the new patch set (#5).
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor it out.
Tested with BUILD_TIMELESS=1, all four variants do not change.
Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 4 files changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43908/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
Patch Set 5:
(2 comments)
Thanks
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... File src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... PS4, Line 132:
empty line
Done
https://review.coreboot.org/c/coreboot/+/43908/4/src/mainboard/intel/kblrvp/... PS4, Line 133: does not match devicetree!
Thanks for the explanation, will remove the FIXME
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
Patch Set 5: Code-Review+2
Hello build bot (Jenkins), Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43908
to look at the new patch set (#6).
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor it out.
Tested with BUILD_TIMELESS=1, all four variants do not change.
Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 4 files changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43908/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
Patch Set 6: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43908 )
Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ......................................................................
mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor it out.
Tested with BUILD_TIMELESS=1, all four variants do not change.
Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43908 Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 4 files changed, 1 insertion(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 0b1ba1d..580f5b0 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -23,6 +23,7 @@ register "dptf_enable" = "1"
# FSP Configuration + register "HeciEnabled" = "0" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 9c9a2e7..4c2225a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -9,7 +9,6 @@ # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 26be7dd..11f9c01 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -13,7 +13,6 @@ register "gen2_dec" = "0x000c0201"
# FSP Configuration - register "HeciEnabled" = "0" register "PmTimerDisabled" = "1"
# VR Settings Configuration for 4 Domains diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 18d764b..25dc49e 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -7,7 +7,6 @@ # FSP Configuration register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
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Felix Singer (Code Review)
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