Change in coreboot[master]: soc/intel/broadwell/acpi: Use the correct last PCI BUS

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35873 )

Change subject: soc/intel/broadwell/acpi: Use the correct last PCI BUS
......................................................................

soc/intel/broadwell/acpi: Use the correct last PCI BUS

Use the correct last PCI BUS number. The MMCONF_BASE is 0xf000000 so
256 busses is most certainly wrong. The bootblock programs it to 64
busses, so the assumption is that the mrc.bin does not modify that.

Change-Id: Id8a8d10e069f2ab6dd5c87d2df462d00c6fad11e
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi.c
2 files changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35873/1

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5856ef1..13fdd55 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -85,6 +85,10 @@
    hex
    default 0xf0000000

+config MMCONF_BUS_NUMBER
+       int
+       default 64
+
 config SMM_TSEG_SIZE
    hex
    default 0x800000
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 7acde68..b5b7f0b 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -219,7 +219,8 @@
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
    current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-					     MCFG_BASE_ADDRESS, 0, 0, 255);
+					     MCFG_BASE_ADDRESS, 0, 0,
+					     CONFIG_MMCONF_BUS_NUMBER - 1);
    return current;
 }

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35873

to look at the new patch set (#2).

Change subject: soc/intel/broadwell/acpi: Use the correct last PCI BUS
......................................................................

soc/intel/broadwell/acpi: Use the correct last PCI BUS

Use the correct last PCI BUS number. The MMCONF_BASE is 0xf000000 so
256 busses is most certainly wrong. The bootblock programs it to 64
busses, so the assumption is that the mrc.bin does not modify that.

Change-Id: Id8a8d10e069f2ab6dd5c87d2df462d00c6fad11e
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi.c
2 files changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35873/2

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35873

to look at the new patch set (#3).

Change subject: soc/intel/broadwell/acpi: Use the correct last PCI BUS
......................................................................

soc/intel/broadwell/acpi: Use the correct last PCI BUS

Use the correct last PCI BUS number. The MMCONF_BASE is 0xf000000 so
256 busses is most certainly wrong. The bootblock programs it to 64
busses, so the assumption is that the mrc.bin does not modify that.

Change-Id: Id8a8d10e069f2ab6dd5c87d2df462d00c6fad11e
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi.c
2 files changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35873/3

[Arthur Heymans (Code Review)]

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35873 )

Change subject: soc/intel/broadwell/acpi: Use the correct last PCI BUS
......................................................................

Abandoned

Fixed in master