[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell/acpi: Use the correct last PCI BUS

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35873

to look at the new patch set (#3).

Change subject: soc/intel/broadwell/acpi: Use the correct last PCI BUS
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soc/intel/broadwell/acpi: Use the correct last PCI BUS

Use the correct last PCI BUS number. The MMCONF_BASE is 0xf000000 so
256 busses is most certainly wrong. The bootblock programs it to 64
busses, so the assumption is that the mrc.bin does not modify that.

Change-Id: Id8a8d10e069f2ab6dd5c87d2df462d00c6fad11e
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi.c
2 files changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35873/3