Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
amd/agesa/family14: implement C bootblock
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ibcaedba030d80a230eecfda6244ca54f7635d0b4 --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/family14/Makefile.inc A src/northbridge/amd/agesa/family14/bootblock.c A src/northbridge/amd/agesa/family14/nb_util.c M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig 8 files changed, 104 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/37331/1
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 9956579..7e180df 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -59,7 +59,7 @@
config S3_DATA_POS hex - default 0xFFFF0000 + default 0xFFFE0000
config S3_DATA_SIZE int diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 518235b..6957b13 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -21,4 +21,16 @@ int default 36
+config AGESA_CAR_HEAP_BASE + hex + default 0x400000 + +config AGESA_HEAP_SIZE + hex + default 0x10000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + endif diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 50dba25..e1e129a 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,7 +17,6 @@ bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP - select ROMCC_BOOTBLOCK
if NORTHBRIDGE_AMD_AGESA
diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index ad39325..ca6439f 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -13,6 +13,13 @@ # GNU General Public License for more details. #
+ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +endif + +bootblock-y += nb_util.c +romstage-y += nb_util.c + romstage-y += dimmSpd.c
ramstage-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c new file mode 100644 index 0000000..8ab789f --- /dev/null +++ b/src/northbridge/amd/agesa/family14/bootblock.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> +#include <device/pci_ops.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 + +#define AGESA_EARLY_VMTRR_FLASH 1 +#define AGESA_EARLY_VMTRR_CAR_HEAP 2 + +void amd_initmmio(void) +{ + msr_t msr; + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + int mtrr; + pci_devfn_t dev; + + msr.hi = 0; + msr.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, msr); + + /* Set Ontario Link Data */ + dev = PCI_DEV(0, 0, 0); + pci_write_config32(dev, 0xE0, 0x01308002); + pci_write_config32(dev, 0xE4, (AMD_APU_SSID << 0x10) | AMD_APU_SVID); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - AGESA_EARLY_VMTRR_FLASH; + set_var_mtrr(mtrr, OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - AGESA_EARLY_VMTRR_CAR_HEAP; + set_var_mtrr(mtrr, CONFIG_AGESA_CAR_HEAP_BASE, + CONFIG_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); + + /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ + msr.lo = 0; + msr.hi = 0; + wrmsr(PS_CTL_REG, msr); +} diff --git a/src/northbridge/amd/agesa/family14/nb_util.c b/src/northbridge/amd/agesa/family14/nb_util.c new file mode 100644 index 0000000..cfb9afc --- /dev/null +++ b/src/northbridge/amd/agesa/family14/nb_util.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#define BIOSRAM_AP_ENTRY 0xec /* 4 bytes */ + +void *get_ap_entry_ptr(void) +{ + return (void *)biosram_read32(BIOSRAM_AP_ENTRY); +} + +void set_ap_entry_ptr(void *entry) +{ + biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); +} diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index a0841eb..32530f4 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool + select ROMCC_BOOTBLOCK
if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 2be2fd3..c7e01ed 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -15,6 +15,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool + select ROMCC_BOOTBLOCK
if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
Patch Set 1:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig File src/cpu/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig@6... PS1, Line 60: config S3_DATA_POS Separate commit for this please. You probably have this done before I am ready to remove this entirely. Or reduce bootblock size to 32KiB. I think we use <2KiB of S3_DATA_SIZE to be honest but that's the more thorough fix for a later date.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/K... File src/northbridge/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/K... PS1, Line 20: select ROMCC_BOOTBLOCK Already done with future rebase.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 21: romstage-y += nb_util.c We probably won't have this file added.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 26: void amd_initmmio(void) We probably want this named better. Neither PCI MMONF or that MTRR setup seems platform-specific.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 41: pci_write_config32(dev, 0xE4, (AMD_APU_SSID << 0x10) | AMD_APU_SVID); This might be just bogus. At least there should be no reason to call this so early and for each core separately.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/nb_util.c:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 19: void *get_ap_entry_ptr(void) I think we will have these two functions implemented in soc/amd/common. I see no reason why these should be per-platform.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family15tn/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 17: select ROMCC_BOOTBLOCK I have pushed patch to flag each board individually to ROMCC_BOOTBLOCK for the transition period.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family16kb/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 18: select ROMCC_BOOTBLOCK as before
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig File src/cpu/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig@6... PS1, Line 60: config S3_DATA_POS
Separate commit for this please. […]
Ack
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 21: romstage-y += nb_util.c
We probably won't have this file added.
When I setup a separate patch for the BIOSRAM for all AMD platforms, yes.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 26: void amd_initmmio(void)
We probably want this named better. Neither PCI MMONF or that MTRR setup seems platform-specific.
Yes, we can carve out MMCONF and MTRR setup to a common function and put some platform-specific call inside
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 41: pci_write_config32(dev, 0xE4, (AMD_APU_SSID << 0x10) | AMD_APU_SVID);
This might be just bogus. […]
As it touches multiple mainboards, wanted to keep backwards compatibility of code flow. I have only apu1 to test it, so not sure about the impact. I remember I had fixes for SVID on apu2 early before AGESA, because it sometimes did not reboot properly.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family15tn/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 17: select ROMCC_BOOTBLOCK
I have pushed patch to flag each board individually to ROMCC_BOOTBLOCK for the transition period.
Thank you, will align with that
Kyösti Mälkki has uploaded a new patch set (#2) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
amd/agesa/family14: implement C bootblock
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ibcaedba030d80a230eecfda6244ca54f7635d0b4 --- M src/cpu/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family14/Makefile.inc A src/northbridge/amd/agesa/family14/bootblock.c 3 files changed, 71 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/37331/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/K... File src/northbridge/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/K... PS1, Line 20: select ROMCC_BOOTBLOCK
Already done with future rebase.
Done
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 21: romstage-y += nb_util.c
When I setup a separate patch for the BIOSRAM for all AMD platforms, yes.
Done
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/nb_util.c:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 19: void *get_ap_entry_ptr(void)
I think we will have these two functions implemented in soc/amd/common. […]
Done
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family15tn/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 17: select ROMCC_BOOTBLOCK
Thank you, will align with that
Done
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family16kb/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 18: select ROMCC_BOOTBLOCK
as before
Done
Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37331
to look at the new patch set (#3).
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
amd/agesa/family14: implement C bootblock
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ibcaedba030d80a230eecfda6244ca54f7635d0b4 --- M src/cpu/amd/agesa/family14/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/37331/3
Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
Abandoned
Squashed with CB:36914
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)