Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig File src/cpu/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig@6... PS1, Line 60: config S3_DATA_POS
Separate commit for this please. […]
Ack
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 21: romstage-y += nb_util.c
We probably won't have this file added.
When I setup a separate patch for the BIOSRAM for all AMD platforms, yes.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 26: void amd_initmmio(void)
We probably want this named better. Neither PCI MMONF or that MTRR setup seems platform-specific.
Yes, we can carve out MMCONF and MTRR setup to a common function and put some platform-specific call inside
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 41: pci_write_config32(dev, 0xE4, (AMD_APU_SSID << 0x10) | AMD_APU_SVID);
This might be just bogus. […]
As it touches multiple mainboards, wanted to keep backwards compatibility of code flow. I have only apu1 to test it, so not sure about the impact. I remember I had fixes for SVID on apu2 early before AGESA, because it sometimes did not reboot properly.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family15tn/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 17: select ROMCC_BOOTBLOCK
I have pushed patch to flag each board individually to ROMCC_BOOTBLOCK for the transition period.
Thank you, will align with that