8 comments:
File src/cpu/amd/agesa/Kconfig:
Patch Set #1, Line 60: config S3_DATA_POS
Separate commit for this please. You probably have this done before I am ready to remove this entirely. Or reduce bootblock size to 32KiB. I think we use <2KiB of S3_DATA_SIZE to be honest but that's the more thorough fix for a later date.
File src/northbridge/amd/agesa/Kconfig:
Patch Set #1, Line 20: select ROMCC_BOOTBLOCK
Already done with future rebase.
File src/northbridge/amd/agesa/family14/Makefile.inc:
Patch Set #1, Line 21: romstage-y += nb_util.c
We probably won't have this file added.
File src/northbridge/amd/agesa/family14/bootblock.c:
Patch Set #1, Line 26: void amd_initmmio(void)
We probably want this named better. Neither PCI MMONF or that MTRR setup seems platform-specific.
Patch Set #1, Line 41: pci_write_config32(dev, 0xE4, (AMD_APU_SSID << 0x10) | AMD_APU_SVID);
This might be just bogus. At least there should be no reason to call this so early and for each core separately.
File src/northbridge/amd/agesa/family14/nb_util.c:
Patch Set #1, Line 19: void *get_ap_entry_ptr(void)
I think we will have these two functions implemented in soc/amd/common. I see no reason why these should be per-platform.
File src/northbridge/amd/agesa/family15tn/Kconfig:
Patch Set #1, Line 17: select ROMCC_BOOTBLOCK
I have pushed patch to flag each board individually to ROMCC_BOOTBLOCK for the transition period.
File src/northbridge/amd/agesa/family16kb/Kconfig:
Patch Set #1, Line 18: select ROMCC_BOOTBLOCK
as before
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