Hello SH Kim,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/40622
to review the following change.
Change subject: mb/google/nightfury: Tune the usb2_port[0] strength ......................................................................
mb/google/nightfury: Tune the usb2_port[0] strength
Update usb2 port strength parameter for usb2_port[0] to improve SI.
BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports
Signed-off-by: Seunghwan Kim sh_.kim@samsung.corp-partner.google.com Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f --- M src/mainboard/google/hatch/variants/nightfury/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40622/1
diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 4b985d9..2c759bc 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -23,7 +23,7 @@ # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY"
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40622 )
Change subject: mb/google/nightfury: Tune the usb2_port[0] strength ......................................................................
Patch Set 1: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40622 )
Change subject: mb/google/nightfury: Tune the usb2_port[0] strength ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40622 )
Change subject: mb/google/nightfury: Tune the usb2_port[0] strength ......................................................................
mb/google/nightfury: Tune the usb2_port[0] strength
Update usb2 port strength parameter for usb2_port[0] to improve SI.
BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports
Signed-off-by: Seunghwan Kim sh_.kim@samsung.corp-partner.google.com Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/nightfury/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 4b985d9..2c759bc 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -23,7 +23,7 @@ # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY"
-
Patrick Georgi (Code Review) -
Paul Menzel (Code Review)
-
shkim (Code Review)
-
Tim Wawrzynczak (Code Review)