Change in coreboot[master]: soc/intel/{cannonlake,icelake}: Add support to get LPSS controllers l...

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cannonlake,icelake}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cannonlake,icelake}: Add support to get LPSS controllers list from SOC

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/soc_chip.h
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/icelake/include/soc/soc_chip.h
4 files changed, 34 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a58a97c..d9342ee 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -22,10 +22,9 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <soc/soc_chip.h>
 #include <string.h>

-#include "chip.h"
-
 static const int serial_io_dev[] = {
    PCH_DEVFN_I2C0,
    PCH_DEVFN_I2C1,
@@ -411,3 +410,10 @@
 {
    printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Return list of SOC LPSS controllers */
+const int *soc_lpss_controllers(int *size)
+{
+	*size = ARRAY_SIZE(serial_io_dev);
+	return serial_io_dev;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/soc_chip.h b/src/soc/intel/cannonlake/include/soc/soc_chip.h
index 3d6f232..118e201 100644
--- a/src/soc/intel/cannonlake/include/soc/soc_chip.h
+++ b/src/soc/intel/cannonlake/include/soc/soc_chip.h
@@ -18,4 +18,6 @@

#include "../../chip.h"

+const int *soc_lpss_controllers(int *size);
+
 #endif /* _SOC_CANNONLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index ac7edd2..8775075 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -50,6 +50,21 @@
    	params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
 }

+static const int serial_io_dev[] = {
+	PCH_DEVFN_I2C0,
+	PCH_DEVFN_I2C1,
+	PCH_DEVFN_I2C2,
+	PCH_DEVFN_I2C3,
+	PCH_DEVFN_I2C4,
+	PCH_DEVFN_I2C5,
+	PCH_DEVFN_GSPI0,
+	PCH_DEVFN_GSPI1,
+	PCH_DEVFN_GSPI2,
+	PCH_DEVFN_UART0,
+	PCH_DEVFN_UART1,
+	PCH_DEVFN_UART2
+};
+
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
@@ -217,3 +232,10 @@
 {
    printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Return list of SOC LPSS controllers */
+const int *soc_lpss_controllers(int *size)
+{
+	*size = ARRAY_SIZE(serial_io_dev);
+	return serial_io_dev;
+}
diff --git a/src/soc/intel/icelake/include/soc/soc_chip.h b/src/soc/intel/icelake/include/soc/soc_chip.h
index 2d996e9..8041383 100644
--- a/src/soc/intel/icelake/include/soc/soc_chip.h
+++ b/src/soc/intel/icelake/include/soc/soc_chip.h
@@ -18,4 +18,6 @@

#include "../../chip.h"

+const int *soc_lpss_controllers(int *size);
+
 #endif /* _SOC_ICELAKE_SOC_CHIP_H_ */

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34136

to look at the new patch set (#2).

Change subject: soc/intel/{cannonlake,icelake}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cannonlake,icelake}: Add support to get LPSS controllers list from SOC

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/soc_chip.h
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/icelake/include/soc/soc_chip.h
4 files changed, 35 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/2

Change in coreboot[master]: soc/intel/*/include: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/*/include: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 3:

This change is ready for review.

Change in coreboot[master]: soc/intel/*/include: Add support to get LPSS controllers list from SOC

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/*/include: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG@8 
PS3, Line 8: 
Please elaborate why this is needed.

Change in coreboot[master]: soc/intel/*/include: Add support to get LPSS controllers list from SOC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/*/include: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 3:

(3 comments)

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... 
File src/soc/intel/apollolake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... 
PS3, Line 22: soc_lpss_controllers
Where is the implementation for apollolake?

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... 
File src/soc/intel/cannonlake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... 
PS3, Line 22: soc_lpss_controllers
Probably better to put this in lpss.h under intel/common?

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... 
File src/soc/intel/skylake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... 
PS3, Line 22: soc_lpss_controllers
Where is the implementation for skylake?

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34136

to look at the new patch set (#4).

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake  platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/4

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 4:

(4 comments)

https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG@8 
PS3, Line 8:
> Please elaborate why this is needed.

Ack

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... 
File src/soc/intel/apollolake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... 
PS3, Line 22: soc_lpss_controllers
> Where is the implementation for apollolake?

do not plan to implement it for APL, since the irq table implementation would be supported CNL onwards

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... 
File src/soc/intel/cannonlake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... 
PS3, Line 22: soc_lpss_controllers
> Probably better to put this in lpss. […]

Ok. Done, moved to common header.

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... 
File src/soc/intel/skylake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... 
PS3, Line 22: soc_lpss_controllers
> Where is the implementation for skylake?

do not plan to implement it for APL, since the irq table implementation would be supported CNL onwards

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34136

to look at the new patch set (#5).

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake  platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/5

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG@8 
PS3, Line 8:
> Ack

Done

https://review.coreboot.org/c/coreboot/+/34136/2/src/soc/intel/cannonlake/fs... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/34136/2/src/soc/intel/cannonlake/fs... 
PS2, Line 415: int
> size_t

Done

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34136

to look at the new patch set (#6).

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake  platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/6

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 6:

(4 comments)

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... 
File src/soc/intel/apollolake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... 
PS3, Line 22: soc_lpss_controllers
> do not plan to implement it for APL, since the irq table implementation would be supported CNL onwar […]

Done

https://review.coreboot.org/c/coreboot/+/34136/2/src/soc/intel/cannonlake/fs... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/34136/2/src/soc/intel/cannonlake/fs... 
PS2, Line 415: int
> Done

Done.

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... 
File src/soc/intel/cannonlake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... 
PS3, Line 22: soc_lpss_controllers
> Ok. Done, moved to common header.

Done

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... 
File src/soc/intel/skylake/include/soc/soc_chip.h:

https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... 
PS3, Line 22: soc_lpss_controllers
> do not plan to implement it for APL, since the irq table implementation would be supported CNL onwar […]

Done

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34136

to look at the new patch set (#7).

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake  platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/7

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Paul Fagerburg (Code Review)]

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 7: Code-Review+1

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

Patch Set 8:

Waiting for previous patches on the stack to merge this.

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34136

to look at the new patch set (#9).

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake  platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/9

Change in coreboot[master]: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34136 )

Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
......................................................................

soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC

This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake  platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Fagerburg 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 31 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Paul Fagerburg: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 3cc426a..0f27c47 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -18,6 +18,7 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <intelblocks/lpss.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <soc/intel/common/vbt.h>
@@ -446,3 +447,10 @@
 {
    printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Return list of SOC LPSS controllers */
+const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
+{
+	*size = ARRAY_SIZE(serial_io_dev);
+	return serial_io_dev;
+}
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index ce162ef..e31e47b 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -18,6 +18,7 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <intelblocks/lpss.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
@@ -45,6 +46,21 @@
    	params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
 }

+static const pci_devfn_t serial_io_dev[] = {
+	PCH_DEVFN_I2C0,
+	PCH_DEVFN_I2C1,
+	PCH_DEVFN_I2C2,
+	PCH_DEVFN_I2C3,
+	PCH_DEVFN_I2C4,
+	PCH_DEVFN_I2C5,
+	PCH_DEVFN_GSPI0,
+	PCH_DEVFN_GSPI1,
+	PCH_DEVFN_GSPI2,
+	PCH_DEVFN_UART0,
+	PCH_DEVFN_UART1,
+	PCH_DEVFN_UART2
+};
+
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
@@ -229,3 +245,10 @@
 {
    printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Return list of SOC LPSS controllers */
+const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
+{
+	*size = ARRAY_SIZE(serial_io_dev);
+	return serial_io_dev;
+}