Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )
Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... PS3, Line 22: soc_lpss_controllers
do not plan to implement it for APL, since the irq table implementation would be supported CNL onwar […]
Done
https://review.coreboot.org/c/coreboot/+/34136/2/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/34136/2/src/soc/intel/cannonlake/fs... PS2, Line 415: int
Done
Done.
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... PS3, Line 22: soc_lpss_controllers
Ok. Done, moved to common header.
Done
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... PS3, Line 22: soc_lpss_controllers
do not plan to implement it for APL, since the irq table implementation would be supported CNL onwar […]
Done