Aamir Bohra has uploaded this change for review.

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soc/intel/{cannonlake,icelake}: Add support to get LPSS controllers list from SOC

Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/soc_chip.h
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/icelake/include/soc/soc_chip.h
4 files changed, 34 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34136/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a58a97c..d9342ee 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -22,10 +22,9 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <soc/soc_chip.h>
 #include <string.h>
 
-#include "chip.h"
-
 static const int serial_io_dev[] = {
 	PCH_DEVFN_I2C0,
 	PCH_DEVFN_I2C1,
@@ -411,3 +410,10 @@
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Return list of SOC LPSS controllers */
+const int *soc_lpss_controllers(int *size)
+{
+	*size = ARRAY_SIZE(serial_io_dev);
+	return serial_io_dev;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/soc_chip.h b/src/soc/intel/cannonlake/include/soc/soc_chip.h
index 3d6f232..118e201 100644
--- a/src/soc/intel/cannonlake/include/soc/soc_chip.h
+++ b/src/soc/intel/cannonlake/include/soc/soc_chip.h
@@ -18,4 +18,6 @@
 
 #include "../../chip.h"
 
+const int *soc_lpss_controllers(int *size);
+
 #endif /* _SOC_CANNONLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index ac7edd2..8775075 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -50,6 +50,21 @@
 		params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
 }
 
+static const int serial_io_dev[] = {
+	PCH_DEVFN_I2C0,
+	PCH_DEVFN_I2C1,
+	PCH_DEVFN_I2C2,
+	PCH_DEVFN_I2C3,
+	PCH_DEVFN_I2C4,
+	PCH_DEVFN_I2C5,
+	PCH_DEVFN_GSPI0,
+	PCH_DEVFN_GSPI1,
+	PCH_DEVFN_GSPI2,
+	PCH_DEVFN_UART0,
+	PCH_DEVFN_UART1,
+	PCH_DEVFN_UART2
+};
+
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
@@ -217,3 +232,10 @@
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Return list of SOC LPSS controllers */
+const int *soc_lpss_controllers(int *size)
+{
+	*size = ARRAY_SIZE(serial_io_dev);
+	return serial_io_dev;
+}
diff --git a/src/soc/intel/icelake/include/soc/soc_chip.h b/src/soc/intel/icelake/include/soc/soc_chip.h
index 2d996e9..8041383 100644
--- a/src/soc/intel/icelake/include/soc/soc_chip.h
+++ b/src/soc/intel/icelake/include/soc/soc_chip.h
@@ -18,4 +18,6 @@
 
 #include "../../chip.h"
 
+const int *soc_lpss_controllers(int *size);
+
 #endif /* _SOC_ICELAKE_SOC_CHIP_H_ */

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