Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34136 )
Change subject: soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34136/3//COMMIT_MSG@8 PS3, Line 8:
Please elaborate why this is needed.
Ack
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/apollolake/in... PS3, Line 22: soc_lpss_controllers
Where is the implementation for apollolake?
do not plan to implement it for APL, since the irq table implementation would be supported CNL onwards
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/cannonlake/in... PS3, Line 22: soc_lpss_controllers
Probably better to put this in lpss. […]
Ok. Done, moved to common header.
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/34136/3/src/soc/intel/skylake/inclu... PS3, Line 22: soc_lpss_controllers
Where is the implementation for skylake?
do not plan to implement it for APL, since the irq table implementation would be supported CNL onwards