Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/1
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2b06a50..f7e2c13 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -9,6 +9,27 @@ /* Forward declare the power state struct here */ struct chipset_power_state;
+/* pmc_ipc_buffer struct declaration to be used for IPC commands */ +struct pmc_ipc_buffer { + uint32_t buf0; + uint32_t buf1; + uint32_t buf2; + uint32_t buf3; +}; + +/* pmc_ipc_cmd union declaration to store cmd data for IPC commands */ +union pmc_ipc_cmd { + uint32_t cmd_reg; + struct { + uint32_t cmd:8; + uint32_t msi:1; + uint32_t res_1:3; + uint32_t subcmd:4; + uint32_t len:8; + uint32_t res_2:8; + }; +}; + /* * This is implemented as weak function in common pmc lib. * Clears all power management related registers as the boot @@ -220,4 +241,10 @@ */ void pmc_set_power_failure_state(bool target_on);
+/* + * Send PMC IPC command + */ +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 12eb38e..818a36b 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <delay.h> #include <halt.h> #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> @@ -16,6 +17,26 @@ #include <stdint.h> #include <string.h> #include <timer.h> +#include <types.h> + +/* define the offsets of all WBUFs */ +#define PMC_IPC_WBUF0 0x80 +#define PMC_IPC_WBUF1 0x84 +#define PMC_IPC_WBUF2 0x88 +#define PMC_IPC_WBUF3 0x8C + +/* define the offsets of all RBUFs */ +#define PMC_IPC_RBUF0 0x90 +#define PMC_IPC_RBUF1 0x94 +#define PMC_IPC_RBUF2 0x98 +#define PMC_IPC_RBUF3 0x9C + +#define PMC_IPC_CMD_OFFSET 0x0 +#define PMC_IPC_USBC_CMD_ID 0xA7 +#define PMC_IPC_STS_OFFSET 0x4 +#define PMC_IPC_STS_BUSY BIT(0) +#define PMC_IPC_STS_ERR BIT(1) +#define PMC_IPC_XFER_TIMEOUT_MS 1000 /* max 1s*/
static struct chipset_power_state power_state;
@@ -574,3 +595,56 @@
pmc_soc_set_afterg3_en(on); } + +static enum cb_err check_ipc_sts(uintptr_t pmcbase) +{ + struct stopwatch sw; + uint32_t ipcsts; + + stopwatch_init_msecs_expire(&sw, PMC_IPC_XFER_TIMEOUT_MS); + do { + ipcsts = read32((void *)(pmcbase + PMC_IPC_STS_OFFSET)); + if (ipcsts & PMC_IPC_STS_ERR) + return CB_ERR; + + udelay(1); + + } while (!stopwatch_expired(&sw) && (ipcsts & PMC_IPC_STS_BUSY)); + + if (ipcsts & PMC_IPC_STS_BUSY) { + printk(BIOS_ERR, "IPC Timeout after %d ms\n", PMC_IPC_XFER_TIMEOUT_MS); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf) +{ + uintptr_t pmcbase; + + pmcbase = soc_read_pmc_base(); + + /* write the entire WBUF with the new PMC CMD Buffer */ + write32((void *)(pmcbase + PMC_IPC_WBUF0), wbuf->buf0); + write32((void *)(pmcbase + PMC_IPC_WBUF1), wbuf->buf1); + write32((void *)(pmcbase + PMC_IPC_WBUF2), wbuf->buf2); + write32((void *)(pmcbase + PMC_IPC_WBUF3), wbuf->buf3); + + /* Write the command register with the new command */ + write32((void *)(pmcbase + PMC_IPC_CMD_OFFSET), cmd); + + if (check_ipc_sts(pmcbase)) { + printk(BIOS_ERR, "PMC IPC command failed\n"); + return CB_ERR; + } + + /* get the response from the pmc out buffer */ + rbuf->buf0 = read32((void *)(pmcbase + PMC_IPC_RBUF0)); + rbuf->buf1 = read32((void *)(pmcbase + PMC_IPC_RBUF1)); + rbuf->buf2 = read32((void *)(pmcbase + PMC_IPC_RBUF2)); + rbuf->buf3 = read32((void *)(pmcbase + PMC_IPC_RBUF3)); + + return CB_SUCCESS; +}
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 1:
Brandon, have you seen the patchsets we ended up with in depthcharge? see the patch train beginning at https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 2:
Patch Set 1:
Brandon, have you seen the patchsets we ended up with in depthcharge? see the patch train beginning at https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...
Going through and updating the patches to reflect what was changed in depthcharge will update the PMC stuff today working on the command sending today and tomorrow as there is a lot more in coreboot with SAFE and DP ALT modes also needed
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42077
to look at the new patch set (#3).
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42077/3/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/3/src/soc/intel/common/block/... PS3, Line 635: IF (IPC_STS_HAS_ERROR(ipc_sts)) { space prohibited between function name and open parenthesis '('
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42077
to look at the new patch set (#4).
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 129 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42077/4/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/4/src/soc/intel/common/block/... PS4, Line 633: IF (IPC_STS_HAS_ERROR(ipc_sts)) { space prohibited between function name and open parenthesis '('
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42077
to look at the new patch set (#5).
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 129 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/5
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... PS5, Line 44: 1000 nit: 1 * MSECS_PER_SEC (see src/include/timer.h)
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 5:
(2 comments)
is any of this tigerlake specific or is intel/common a good place for this?
https://review.coreboot.org/c/coreboot/+/42077/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42077/5//COMMIT_MSG@13 PS5, Line 13: 141608957 151731851?
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... PS5, Line 29: RBUT typo
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42077/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42077/5//COMMIT_MSG@15 PS5, Line 15: TEST: TEST=
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... PS5, Line 640: udelay(50); blank line after if statement please
Hello build bot (Jenkins), Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42077
to look at the new patch set (#6).
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 130 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/6
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/42077/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42077/5//COMMIT_MSG@13 PS5, Line 13: 141608957
151731851?
Yeah seems I still was referencing the old bug
https://review.coreboot.org/c/coreboot/+/42077/5//COMMIT_MSG@15 PS5, Line 15: TEST:
TEST=
Done
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... PS5, Line 29: RBUT
typo
Done
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... PS5, Line 44: 1000
nit: 1 * MSECS_PER_SEC (see src/include/timer. […]
Done
https://review.coreboot.org/c/coreboot/+/42077/5/src/soc/intel/common/block/... PS5, Line 640: udelay(50);
blank line after if statement please
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 47: one more tab to line up with line above
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 610: const uintptr_t pmcbase = soc_read_pmc_base(); : return (void *)(pmcbase + pmc_reg_offset); I think `return (soc_read_pmc_base() + pmc_reg_offset);` would be enough, the cast to `void *` is not necessary
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 624: enum cb_err nit: no need to use cb_err for static functions, it's more for exported APIs
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 44: */ nit: space before the comment closing
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 610: const uintptr_t pmcbase = soc_read_pmc_base(); : return (void *)(pmcbase + pmc_reg_offset);
I think `return (soc_read_pmc_base() + pmc_reg_offset);` would be enough, the cast to `void *` is no […]
The cast is because readX / writeX functions take a pointer
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 610: const uintptr_t pmcbase = soc_read_pmc_base(); : return (void *)(pmcbase + pmc_reg_offset);
The cast is because readX / writeX functions take a pointer
Oh that's right, uintptr_t isn't an actual pointer type.
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 44: */
nit: space before the comment closing
Done
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 47:
one more tab to line up with line above
Done
https://review.coreboot.org/c/coreboot/+/42077/6/src/soc/intel/common/block/... PS6, Line 624: enum cb_err
nit: no need to use cb_err for static functions, it's more for exported APIs
Done
Hello build bot (Jenkins), Caveh Jalali, Duncan Laurie, Nick Vaccaro, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42077
to look at the new patch set (#7).
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 130 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42077/7/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/7/src/soc/intel/common/block/... PS7, Line 48: PMC_IPC_ERR_CODE_MASK)) code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42077/7/src/soc/intel/common/block/... PS7, Line 48: PMC_IPC_ERR_CODE_MASK)) please, no space before tabs
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42077/8/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/8/src/soc/intel/common/block/... PS8, Line 48: PMC_IPC_ERR_CODE_MASK)) code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42077/8/src/soc/intel/common/block/... PS8, Line 48: PMC_IPC_ERR_CODE_MASK)) please, no space before tabs
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 8: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/42077/8/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/42077/8/src/soc/intel/common/block/... PS8, Line 247: PMC_IPC_CMD_FIELD(MSI, PMC_IPC_CMD_NO_MSI) nit: this is just always 0
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42077/9/src/soc/intel/common/block/... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/9/src/soc/intel/common/block/... PS9, Line 48: PMC_IPC_ERR_CODE_MASK)) code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42077/9/src/soc/intel/common/block/... PS9, Line 48: PMC_IPC_ERR_CODE_MASK)) please, no space before tabs
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42077/10/src/soc/intel/common/block... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/42077/10/src/soc/intel/common/block... PS10, Line 47: PMC_IPC_ERR_CODE_MASK)) code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42077/10/src/soc/intel/common/block... PS10, Line 47: PMC_IPC_ERR_CODE_MASK)) please, no space before tabs
Hello build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Nick Vaccaro, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42077
to look at the new patch set (#11).
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 130 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/11
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 11: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42077/8/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/42077/8/src/soc/intel/common/block/... PS8, Line 247: PMC_IPC_CMD_FIELD(MSI, PMC_IPC_CMD_NO_MSI)
nit: this is just always 0
Ack
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 11:
needs rebase
Duncan Laurie has uploaded a new patch set (#12) to the change originally created by Brandon Breitenstein. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- A src/soc/intel/common/block/include/intelblocks/pmc_ipc.h M src/soc/intel/common/block/pmc/Makefile.inc A src/soc/intel/common/block/pmc/pmc_ipc.c 3 files changed, 146 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/12
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 12:
Patch Set 11:
needs rebase
Done. I also moved this to a new file as I have a change that builds on it (acpi interface for rtd3) and it seems to be outgrowing pmclib.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
Patch Set 12: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42077 )
Change subject: soc/intel/common/block: Enable PMC IPC driver ......................................................................
soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states.
BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42077 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- A src/soc/intel/common/block/include/intelblocks/pmc_ipc.h M src/soc/intel/common/block/pmc/Makefile.inc A src/soc/intel/common/block/pmc/pmc_ipc.c 3 files changed, 146 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h new file mode 100644 index 0000000..0c90cd7 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PMC_IPC_H +#define SOC_INTEL_COMMON_BLOCK_PMC_IPC_H + +#include <types.h> + +#define PMC_IPC_BUF_COUNT 4 + +#define PMC_IPC_CMD_COMMAND_SHIFT 0 +#define PMC_IPC_CMD_COMMAND_MASK 0xff +#define PMC_IPC_CMD_MSI_SHIFT 8 +#define PMC_IPC_CMD_MSI_MASK 0x01 +#define PMC_IPC_CMD_SUB_COMMAND_SHIFT 12 +#define PMC_IPC_CMD_SUB_COMMAND_MASK 0x0f +#define PMC_IPC_CMD_SIZE_SHIFT 16 +#define PMC_IPC_CMD_SIZE_MASK 0xff + +#define PMC_IPC_CMD_FIELD(name, val) \ + (((val) & PMC_IPC_CMD_##name##_MASK << PMC_IPC_CMD_##name##_SHIFT)) + +#define PMC_IPC_CMD_NO_MSI 0 + +/* + * Create the IPC CMD to send to PMC + */ +static inline uint32_t pmc_make_ipc_cmd(uint32_t cmd, uint32_t subcmd, + uint32_t size) +{ + return PMC_IPC_CMD_FIELD(COMMAND, cmd) | + PMC_IPC_CMD_FIELD(SUB_COMMAND, subcmd) | + PMC_IPC_CMD_FIELD(MSI, PMC_IPC_CMD_NO_MSI) | + PMC_IPC_CMD_FIELD(SIZE, size); +} + +/* + * Buffer for holding write and read buffers of IPC commands + */ +struct pmc_ipc_buffer { + uint32_t buf[PMC_IPC_BUF_COUNT]; +}; + +/* + * Send PMC IPC command + */ +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf); + +#endif /* SOC_INTEL_COMMON_BLOCK_PMC_IPC_H */ diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc index 9657217..796a039 100644 --- a/src/soc/intel/common/block/pmc/Makefile.inc +++ b/src/soc/intel/common/block/pmc/Makefile.inc @@ -2,7 +2,7 @@ bootblock-y += pmclib.c romstage-y += pmclib.c ramstage-y += pmc.c -ramstage-y += pmclib.c +ramstage-y += pmclib.c pmc_ipc.c smm-y += pmclib.c verstage-y += pmclib.c postcar-y += pmclib.c diff --git a/src/soc/intel/common/block/pmc/pmc_ipc.c b/src/soc/intel/common/block/pmc/pmc_ipc.c new file mode 100644 index 0000000..7decf79 --- /dev/null +++ b/src/soc/intel/common/block/pmc/pmc_ipc.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/pmc_ipc.h> +#include <stdint.h> +#include <timer.h> + +/* + * WBUF register block offset 0x80..0x8f there are 4 consecutive + * 32 bit registers + */ +#define IPC_WBUF0 0x80 + +/* + * RBUF registers block offset 0x90..0x9f there are 4 consecutive + * 32 bit registers + */ +#define IPC_RBUF0 0x90 + +/* + * From Intel 500 Series PCH EDS vol2 s4.4 + */ +#define PMC_IPC_CMD_OFFSET 0x0 +#define PMC_IPC_STS_OFFSET 0x4 +#define PMC_IPC_STS_BUSY BIT(0) +#define PMC_IPC_STS_ERR BIT(1) +#define PMC_IPC_ERR_CODE_SHIFT 16 +#define PMC_IPC_ERR_CODE_MASK 0xff + +#define PMC_IPC_XFER_TIMEOUT_MS (1 * MSECS_PER_SEC) /* max 1s */ +#define IS_IPC_STS_BUSY(status) ((status) & PMC_IPC_STS_BUSY) +#define IPC_STS_HAS_ERROR(status) ((status) & PMC_IPC_STS_ERR) +#define IPC_STS_ERROR_CODE(sts) (((sts) >> PMC_IPC_ERR_CODE_SHIFT & \ + PMC_IPC_ERR_CODE_MASK)) + +static void *pmc_reg(unsigned int pmc_reg_offset) +{ + const uintptr_t pmcbase = soc_read_pmc_base(); + return (void *)(pmcbase + pmc_reg_offset); +} + +static const void *pmc_rbuf(unsigned int ix) +{ + return pmc_reg(IPC_RBUF0 + ix * sizeof(uint32_t)); +} + +static void *pmc_wbuf(unsigned int ix) +{ + return pmc_reg(IPC_WBUF0 + ix * sizeof(uint32_t)); +} + +static int check_ipc_sts(void) +{ + struct stopwatch sw; + uint32_t ipc_sts; + + stopwatch_init_msecs_expire(&sw, PMC_IPC_XFER_TIMEOUT_MS); + do { + ipc_sts = read32(pmc_reg(PMC_IPC_STS_OFFSET)); + if (!(IS_IPC_STS_BUSY(ipc_sts))) { + if (IPC_STS_HAS_ERROR(ipc_sts)) { + printk(BIOS_ERR, "IPC_STS.error_code 0x%x\n", + IPC_STS_ERROR_CODE(ipc_sts)); + return -1; + } + return 0; + } + udelay(50); + + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "PMC IPC timeout after %u ms\n", PMC_IPC_XFER_TIMEOUT_MS); + return -1; +} + +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf) +{ + for (int i = 0; i < PMC_IPC_BUF_COUNT; ++i) + write32(pmc_wbuf(i), wbuf->buf[i]); + + write32(pmc_reg(PMC_IPC_CMD_OFFSET), cmd); + + if (check_ipc_sts()) { + printk(BIOS_ERR, "PMC IPC command 0x%x failed\n", cmd); + return CB_ERR; + } + + for (int i = 0; i < PMC_IPC_BUF_COUNT; ++i) + rbuf->buf[i] = read32(pmc_rbuf(i)); + + return CB_SUCCESS; +}
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Angel Pons (Code Review) -
Brandon Breitenstein (Code Review)
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build bot (Jenkins) (Code Review)
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Caveh Jalali (Code Review)
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Duncan Laurie (Code Review)
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Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)