Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

[Shreesh Chhabbi (Code Review)]

Hello Shreesh Chhabbi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/47259

to review the following change.

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index ed35bd6..8d88b7b 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -23,7 +23,8 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE
-	select INTEL_CAR_NEM
+	select INTEL_CAR_NEM if !INTEL_CAR_NEM_ENHANCED
+	select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select IOAPIC

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#2) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
is selected in Tigerlake soc Kconfig.

Kconfig was missing the selection of

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/2

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#3) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
is selected in Tigerlake soc Kconfig.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/3

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#4) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
is selected in Tigerlake soc Kconfig.

Bug=none
Test=Build Coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/4

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#5) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
is selected in Tigerlake soc Kconfig.

Bug=b:171601324
Test=Build Coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/5

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#6) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
is selected in Tigerlake soc Kconfig.

Bug=b/171601324
Test=Build Coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/6

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#7) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
is selected in Tigerlake soc Kconfig.

Bug=171601324
Test=Build Coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/7

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@13 
PS7, Line 13: Coreboot
Hi Shreesh, the word 'coreboot' needs to be lowercase.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 
PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
           : is selected in Tigerlake soc Kconfig.
I think it would be good to add some more details explaining why this change is being made and how this will change again once things are better understood after SF_MASK. Also, are you planning on adding the Kconfigs as discussed here: b/172592700

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 
PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
           : is selected in Tigerlake soc Kconfig.
> I think it would be good to add some more details explaining why this change is being made and how t […]

Ack

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@13 
PS7, Line 13: Coreboot
> Hi Shreesh, the word 'coreboot' needs to be lowercase.

Ack

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 
PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
           : is selected in Tigerlake soc Kconfig.
> Ack

I don't really see anything different in the latest patchset. Missed pushing the latest changes?

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#9) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.

Bug=171601324
Test=Build Coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/9

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 9:

(2 comments)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 
PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
           : is selected in Tigerlake soc Kconfig.
> I don't really see anything different in the latest patchset. […]

Initially I only selected "ack" Furquan. That update notified you. I changed commit message now. Please help to review.

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@13 
PS7, Line 13: Coreboot
> Ack

Changed it to lower case. Thanks.

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#10) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.

Bug=171601324
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/10

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 
PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
           : is selected in Tigerlake soc Kconfig.
> Initially I only selected "ack" Furquan. That update notified you. I changed commit message now. […]

Furquan while I was making code changes, I realized that the change you have made is appropriate. _V1 and _V2 both select INTEL_CAR_NEM_ENHANCED in cpu/Kconfig. So its better to check for INTEL_CAR_NEM_ENHANCED for selecting COS_MAPPED_TO_MSB.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 10:

(3 comments)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 
PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
           : is selected in Tigerlake soc Kconfig.
> Furquan while I was making code changes, I realized that the change you have made is appropriate. […]

That sounds okay. BTW, as I was reviewing this and following change again I realized that it might be better to do the following since you anyways have to touch both SoC and mainboard Kconfig files:

CL-1: Flip the selection of INTEL_CAR_NEM and INTEL_CAR_NEM_ENHANCED_V2 between mainboard and SoC. i.e. update all TGL boards that are not selecting INTEL_CAR_NEM_ENHANCED_V2 right now to select INTEL_CAR_NEM. And select INTEL_CAR_NEM_ENHANCED_V2 in SoC/Kconfig if INTEL_CAR_NEM is not selected. This will make it easier to flip the NEM enhanced versions at the SoC level without having to make any changes in mainboard in the future. Also, when a board deprecates support for the earlier silicon, it can just drop the selection of INTEL_CAR_NEM. (P.S. You will need to update both volteer and tglrvp).

CL-2: Switch TGL to using INTEL_CAR_NEM_ENHANCED_V1 and select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED is selected. You can add the reasoning in commit message that we are selecting V1 because the SF mask programming required is still being investigated.

Sorry about the back and forth. I think with the above changes, we will make it easier to handle the update of NEM enhanced at the SoC level in the future.

https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@14 
PS10, Line 14: 171601324
This should be b:171601324

https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@15 
PS10, Line 15: Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
BRANCH=volteer

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#11) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.

Bug=b:171601324
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/11

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#12) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/12

[Shreesh Chhabbi (Code Review)]

Hello build bot (Jenkins), Caveh Jalali, Shreesh Chhabbi, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47259

to look at the new patch set (#13).

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/13

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
PS13, Line 26: USE_CAR_NEM_ENHANCED_V1
You will need the mainboard Kconfig changes in the same file to ensure that the selection is correct for all boards.

Also, I think it would be good to start with USE_CAR_NEM_ENHANCED_V2 in this CL and switch to USE_CAR_NEM_ENHANCED_V1 in follow-up CL so that this change is only about flipping the configs while keeping the functionality same. And the follow-up CL will actually switch from V2 to V1.

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
PS13, Line 26: USE_CAR_NEM_ENHANCED_V1
> You will need the mainboard Kconfig changes in the same file to ensure that the selection is correct […]

In the other CL, I selected INTEL_CAR_NEM for the boards using ESx. I did not select anything for boards using QS. I was about push that update for other CL. In such case, USE_CAR_NEM_ENHANCED_V1 selected in soc/Kconfig would be the final change, right? Are you suggesting to select USE_CAR_NEM_ENHANCED_V1 in volteer/Kconfig.name for boards using QS?

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
PS13, Line 26: USE_CAR_NEM_ENHANCED_V1
> In the other CL, I selected INTEL_CAR_NEM for the boards using ESx. […]

So, basically there would be two CLs:

** First CL: **
soc/intel/tigerlake/Kconfig 
  --> Use `select INTEL_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM` instead of `select INTEL_CAR_NEM`
mainboard/google/volteer/Kconfig.name
  --> Drop `select INTEL_CAR_NEM_ENHANCED_V2` from the variants selecting it.
  --> Add `select INTEL_CAR_NEM` to all variants that were not selecting INTEL_CAR_NEM_ENHANCED_V2 before
mainboard/intel/tglrvp/Kconfig
  --> Add `select INTEL_CAR_NEM` since it is not selecting INTEL_CAR_NEM_ENHANCED_V2

** Second CL: **
soc/intel/tigerlake/Kconfig
  --> Use `select INTEL_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM` instead of `select INTEL_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM`
  --> Add `select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED`
(For second CL you can add the information about why we are switching to V1 and how this will be fixed once SF mask configuration is figured out)

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
PS13, Line 26: USE_CAR_NEM_ENHANCED_V1
> In the other CL, I selected INTEL_CAR_NEM for the boards using ESx. […]

Hi Furquan, please review both CLs now if they look ok. Summary is as below.

CL 47259:
soc/Kconfig - 
Selecting USE_CAR_NEM_ENHANCED_V1
Selecting COS_MAPPED_TO_MSB

CL 47258:
volteer/Kconfig.name -
Selecting INTEL_CAR_NEM for all ESx boards.

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
PS13, Line 26: USE_CAR_NEM_ENHANCED_V1
> Hi Furquan, please review both CLs now if they look ok. Summary is as below. […]

I got your point now. I will update.

[Shreesh Chhabbi (Code Review)]

Hello build bot (Jenkins), Caveh Jalali, Shreesh Chhabbi, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47259

to look at the new patch set (#14).

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
M src/soc/intel/tigerlake/Kconfig
2 files changed, 8 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/14

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 14: Code-Review+2

(2 comments)

https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG@9 
PS14, Line 9: IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
            : when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
            : INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
            : COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.
This needs update now.

This change switches the selection of CAR mode so that INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by mainboards using older silicon that did not support NEM enhanced.

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
File src/mainboard/google/volteer/Kconfig.name:

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
PS14, Line 18: INTEL_CAR_NEM
You will need this for tglrvp too.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 14: Code-Review+1

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 14: Code-Review+1

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 14:

Hi Patrick, Martin, could you please submit merge patch?

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 14:
> Patch Set 14:
>
> Hi Patrick, Martin, could you please submit merge patch?

You still need to address:
https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG#12
https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte...

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
File src/mainboard/google/volteer/Kconfig.name:

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
PS14, Line 18: INTEL_CAR_NEM
> You will need this for tglrvp too.

Hi Furquan, Tim, for TGL RVP, I kept NEM Enhanced Mode enabled as well. We are also using QS. We can enable it.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
File src/mainboard/google/volteer/Kconfig.name:

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
PS14, Line 18: INTEL_CAR_NEM
> Hi Furquan, Tim, for TGL RVP, I kept NEM Enhanced Mode enabled as well. We are also using QS. […]

Sounds good. It would be good to put this in the commit message since it is a change in functionality from before.

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#15) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.
This enables NEM Enhanced Mode for TGL-U/Y RVPs.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
M src/soc/intel/tigerlake/Kconfig
2 files changed, 8 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/15

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG@9 
PS14, Line 9: IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
            : when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
            : INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
            : COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.
> This needs update now. […]

Can you please address this as well?

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
File src/mainboard/google/volteer/Kconfig.name:

https://review.coreboot.org/c/coreboot/+/47259/14/src/mainboard/google/volte... 
PS14, Line 18: INTEL_CAR_NEM
> Sounds good. […]

I agree, updated the commit message.

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 15:

(5 comments)

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 
PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
           : is selected in Tigerlake soc Kconfig.
> That sounds okay. […]

Done

https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@14 
PS10, Line 14: 171601324
> This should be b:171601324

Done

https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@15 
PS10, Line 15: Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
> BRANCH=volteer

Done

https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG@9 
PS14, Line 9: IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
            : when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
            : INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
            : COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.
> Can you please address this as well?

Done

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... 
PS13, Line 26: USE_CAR_NEM_ENHANCED_V1
> I got your point now. I will update.

Done

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#16) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

This change switches the selection of CAR mode so that
INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard
selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by
mainboards using older silicon (ES1 or ES2) that did not
support NEM enhanced.

This enables NEM Enhanced Mode for TGL-U/Y RVPs.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
M src/soc/intel/tigerlake/Kconfig
2 files changed, 8 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/16

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#17) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

This change switches the selection of CAR mode so that
INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard
selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by
mainboards using older silicon (ES1 or ES2) that did not
support NEM enhanced mode.

This enables NEM Enhanced Mode for TGL-U/Y RVPs.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
M src/soc/intel/tigerlake/Kconfig
2 files changed, 8 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/17

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

Patch Set 17: Code-Review+2

Thanks Shreesh!

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
......................................................................

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

This change switches the selection of CAR mode so that
INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard
selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by
mainboards using older silicon (ES1 or ES2) that did not
support NEM enhanced mode.

This enables NEM Enhanced Mode for TGL-U/Y RVPs.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47259
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/google/volteer/Kconfig.name
M src/soc/intel/tigerlake/Kconfig
2 files changed, 8 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Shreesh Chhabbi: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name
index 7aaaea7..b651430 100644
--- a/src/mainboard/google/volteer/Kconfig.name
+++ b/src/mainboard/google/volteer/Kconfig.name
@@ -4,58 +4,60 @@
    bool "-> Delbin"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
    select DRIVERS_GENESYSLOGIC_GL9755

config BOARD_GOOGLE_ELDRID
    bool "-> Eldrid"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2

config BOARD_GOOGLE_HALVOR
    bool "-> Halvor"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
+	select INTEL_CAR_NEM

config BOARD_GOOGLE_LINDAR
    bool "-> Lindar"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
+	select INTEL_CAR_NEM

config BOARD_GOOGLE_MALEFOR
    bool "-> Malefor"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
+	select INTEL_CAR_NEM

config BOARD_GOOGLE_TERRADOR
    bool "-> Terrador"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2

config BOARD_GOOGLE_TODOR
    bool "-> Todor"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
+	select INTEL_CAR_NEM

config BOARD_GOOGLE_TRONDO
    bool "-> Trondo"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
+	select INTEL_CAR_NEM

config BOARD_GOOGLE_VOLTEER
    bool "-> Volteer"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select VARIANT_HAS_MIPI_CAMERA
    select SOC_INTEL_CSE_LITE_SKU
+	select INTEL_CAR_NEM

config BOARD_GOOGLE_VOLTEER2
    bool "-> Volteer2"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select VARIANT_HAS_MIPI_CAMERA
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
    select DRIVERS_GENESYSLOGIC_GL9755

# Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board
@@ -64,27 +66,24 @@
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select VARIANT_HAS_MIPI_CAMERA
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
    select DRIVERS_GENESYSLOGIC_GL9755

config BOARD_GOOGLE_VOXEL
    bool "-> Voxel"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2

config BOARD_GOOGLE_BOLDAR
    bool "-> Boldar"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
+	select INTEL_CAR_NEM

config BOARD_GOOGLE_ELEMI
    bool "-> Elemi"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2

config BOARD_GOOGLE_VOEMA
    bool "-> Voema"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 79a4c64..b276fb9 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -23,7 +23,7 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE
-	select INTEL_CAR_NEM
+	select USE_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select IOAPIC