Shreesh Chhabbi uploaded patch set #10 to the change originally created by Shreesh Chhabbi.

View Change

soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.

Bug=171601324
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/10

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