Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31356
Change subject: WIP: libpayload: add initial support for RISC-V ......................................................................
WIP: libpayload: add initial support for RISC-V
Parse fdt provided by a2 and extract coreboot tables from it.
Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Signed-off-by: Philipp Hug philipp@hug.cx --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c A payloads/libpayload/arch/riscv/sysinfo.c A payloads/libpayload/arch/riscv/timer.c A payloads/libpayload/arch/riscv/util.S A payloads/libpayload/arch/riscv/virtual.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.riscv A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h 22 files changed, 1,094 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31356/1
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 5bfbd54..846280d 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -119,6 +119,11 @@ help Support the MIPS architecture
+config ARCH_RISCV + bool "RISCV" + help + Support the RISCV architecture + endchoice
config MULTIBOOT @@ -148,12 +153,13 @@ default 0x04000000 if ARCH_ARM default 0x80100000 if ARCH_ARM64 default 0x00000000 if ARCH_MIPS + default 0x81000000 if ARCH_RISCV default 0x00100000 if ARCH_X86 help This is the base address for the payload.
If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS, - 0x04000000 on ARM or 0x80100000 on ARM64. + 0x04000000 on ARM or 0x80100000 on ARM64 or 0x81000000 on RISCV.
endmenu
@@ -451,4 +457,5 @@ source "arch/arm/Kconfig" source "arch/arm64/Kconfig" source "arch/mips/Kconfig" +source "arch/riscv/Kconfig" source "arch/x86/Kconfig" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 1a0acf1..e01115e 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -96,6 +96,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
ARCH-y := $(ARCHDIR-y) @@ -105,6 +106,7 @@ ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_RISCV) := riscv ARCH-$(CONFIG_LP_ARCH_MIPS) := mips
# Three cases where we don't need fully populated $(obj) lists: diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 052a3f0..8ea0810 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -34,6 +34,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 DESTDIR ?= install
@@ -61,12 +62,15 @@
INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h
+ARCHCFLAGS-$(CONFIG_LP_ARCH_RISCV) := -mcmodel=medany + CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS += -Wstrict-aliasing -Wshadow -Werror +CFLAGS += $(ARCHCFLAGS-y)
$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ diff --git a/payloads/libpayload/arch/riscv/Kconfig b/payloads/libpayload/arch/riscv/Kconfig new file mode 100644 index 0000000..6352ff0 --- /dev/null +++ b/payloads/libpayload/arch/riscv/Kconfig @@ -0,0 +1,37 @@ +## +## This file is part of the libpayload project. +## +## Copyright (c) 2012 Google Inc. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +if ARCH_RISCV + +config ARCH_SPECIFIC_OPTIONS # dummy + def_bool y + select LITTLE_ENDIAN + select FDT + +endif diff --git a/payloads/libpayload/arch/riscv/Makefile.inc b/payloads/libpayload/arch/riscv/Makefile.inc new file mode 100644 index 0000000..01d6bd8 --- /dev/null +++ b/payloads/libpayload/arch/riscv/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the libpayload project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +head.o-y += head.S + +libc-y += main.c sysinfo.c +libc-y += timer.c coreboot.c util.S +libc-y += virtual.c diff --git a/payloads/libpayload/arch/riscv/coreboot.c b/payloads/libpayload/arch/riscv/coreboot.c new file mode 100644 index 0000000..ea21c51 --- /dev/null +++ b/payloads/libpayload/arch/riscv/coreboot.c @@ -0,0 +1,94 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2019 Philipp Hug philipp@hug.cx + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <coreboot_tables.h> +#include <libfdt.h> + +/* This pointer gets set in head.S and is passed in from coreboot. */ +void *fdt_ptr; +int hart_id; + +/* == Architecture specific == */ + +int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) +{ + switch (rec->tag) { + default: + return 0; + } + return 1; +} + +int get_coreboot_info(struct sysinfo_t *info) +{ + void *cb_header_ptr = get_cb_header_ptr(); + if (cb_header_ptr == NULL) + return 1; + return cb_parse_header(cb_header_ptr, 1, info); +} + +void *get_cb_header_ptr(void) +{ + int offset; + int len; + const struct fdt_property *prop; + + /* + * coreboot tables are provides within the fdt which was passes as + * a2 to the entry point + */ + + if (fdt_check_header(fdt_ptr) != 0) { + printf("fdt: invalid header\n"); + return NULL; + } + + // search for coreboot node + offset = fdt_node_offset_by_compatible(fdt_ptr, -1, "coreboot"); + if (offset < 0) { + printf("fdt: coreboot node not found\n"); + return NULL; + } + + /* + * get reg property and extract the pointer to the coreboot tables + * TODO: parse cell info and fix for RV32 + */ + prop = fdt_get_property(fdt_ptr, offset, "reg", &len); + if (len != 32) { + printf("fdt: invalid reg property\n"); + return NULL; + } + + return (void *)fdt64_ld((fdt64_t *)prop->data); +} diff --git a/payloads/libpayload/arch/riscv/head.S b/payloads/libpayload/arch/riscv/head.S new file mode 100644 index 0000000..c46b20b --- /dev/null +++ b/payloads/libpayload/arch/riscv/head.S @@ -0,0 +1,74 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Philipp Hug philipp@hug.cx + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +/* + * Our entry point + */ +ENTRY(_entry) + + /* Save off hart id in a0 */ + la t0, hart_id + sd a0, 0(t0) + + /* Save off device tree pointer in a1 */ + la t0, fdt_ptr + sd a1, 0(t0) + + /* + * busy-loop for harts != 0 + * TODO: add support hart > 0 + */ + li a3, 0 + beq a0, a3, _hart_zero +_hart_loop: + j _hart_loop +_hart_zero: + + /* + * Setup new stack + * TODO, use stack per hart + */ + la t0, _stack + li t1, 0xDEADBEEF + sd t1, 0(t0) + add sp, t0, 0 + + /* Let's rock. */ + tail start_main + +ENDPROC(_entry) + +.align 4 +1: +.quad fdt_ptr +2: +.quad _stack diff --git a/payloads/libpayload/arch/riscv/libpayload.ldscript b/payloads/libpayload/arch/riscv/libpayload.ldscript new file mode 100644 index 0000000..1929549 --- /dev/null +++ b/payloads/libpayload/arch/riscv/libpayload.ldscript @@ -0,0 +1,91 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv","elf64-littleriscv") +OUTPUT_ARCH(riscv) + +ENTRY(_entry) + +SECTIONS +{ + . = CONFIG_LP_BASE_ADDRESS; + + . = ALIGN(16); + _start = .; + + .text : { + *(.text._entry) + *(.text) + *(.text.*) + } + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + .data : { + *(.data) + *(.data.*) + } + + _edata = .; + + .bss : { + *(.sbss) + *(.sbss.*) + *(.bss) + *(.bss.*) + *(COMMON) + + /* Stack and heap */ + + . = ALIGN(16); + _heap = .; + . += CONFIG_LP_HEAP_SIZE; + . = ALIGN(16); + _eheap = .; + + _estack = .; + . += CONFIG_LP_STACK_SIZE; + . = ALIGN(16); + _stack = .; + } + .debug : { + *(.debug) + } + + _end = .; + + /DISCARD/ : { + *(.comment) + *(.note*) + } +} diff --git a/payloads/libpayload/arch/riscv/main.c b/payloads/libpayload/arch/riscv/main.c new file mode 100644 index 0000000..83fb841 --- /dev/null +++ b/payloads/libpayload/arch/riscv/main.c @@ -0,0 +1,72 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +unsigned int main_argc; /**< The argc value to pass to main() */ + +/** The argv value to pass to main() */ +char *main_argv[MAX_ARGC_COUNT]; + +/** + * This is our C entry function - set up the system + * and jump into the payload entry point. + */ +void start_main(void); +void start_main(void) +{ + extern int main(int argc, char **argv); + + /* Gather system information. */ + lib_get_sysinfo(); + +#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT) + console_init(); +#endif + + // TODO: implement exceptions + // exception_init(); + + /* + * Any other system init that has to happen before the + * user gets control goes here. + */ + + /* + * Go to the entry point. + * In the future we may care about the return value. + */ + + (void)main(main_argc, (main_argc != 0) ? main_argv : NULL); + + /* + * Returning here will go to the _leave function to return + * us to the original context. + */ +} diff --git a/payloads/libpayload/arch/riscv/sysinfo.c b/payloads/libpayload/arch/riscv/sysinfo.c new file mode 100644 index 0000000..575b7da --- /dev/null +++ b/payloads/libpayload/arch/riscv/sysinfo.c @@ -0,0 +1,79 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <coreboot_tables.h> + +/** + * This is a global structure that is used through the library - we set it + * up initially with some dummy values - hopefully they will be overridden. + * Also set some defaults for the console in case the fdt is messed up. + */ +struct cb_serial serial_info = { + .baseaddr = 0x10000000, + .type = CB_SERIAL_TYPE_MEMORY_MAPPED, + .regwidth = 1, +}; + +struct sysinfo_t lib_sysinfo = { + .cpu_khz = 1000, + .serial = &serial_info, +}; + +int lib_get_sysinfo(void) +{ + int ret; + + /* Get the CPU speed (for delays). */ + lib_sysinfo.cpu_khz = get_cpu_speed(); + + /* Get information from the coreboot tables, + * if they exist */ + + ret = get_coreboot_info(&lib_sysinfo); + + if (!lib_sysinfo.n_memranges) { + /* If we can't get a good memory range, use the default. */ + lib_sysinfo.n_memranges = 1; + + lib_sysinfo.memrange[0].base = 0x80000000u; + lib_sysinfo.memrange[0].size = 1024 * 1024; + lib_sysinfo.memrange[0].type = CB_MEM_RAM; + } + + return ret; +} + +void lib_sysinfo_get_memranges(struct memrange **ranges, + uint64_t *nranges) +{ + *ranges = &lib_sysinfo.memrange[0]; + *nranges = lib_sysinfo.n_memranges; +} diff --git a/payloads/libpayload/arch/riscv/timer.c b/payloads/libpayload/arch/riscv/timer.c new file mode 100644 index 0000000..d233ddc --- /dev/null +++ b/payloads/libpayload/arch/riscv/timer.c @@ -0,0 +1,54 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/** + * @file riscv/timer.c + * RISC-V specific timer routines + */ + +#include <libpayload.h> + +/** + * @ingroup arch + * Global variable containing the speed of the processor in KHz. + */ +u32 cpu_khz; + +/** + * Calculate the speed of the processor for use in delays. + * + * @return The CPU speed in kHz. + */ +unsigned int get_cpu_speed(void) +{ + /* FIXME */ + cpu_khz = 1000000U; + + return cpu_khz; +} diff --git a/payloads/libpayload/arch/riscv/util.S b/payloads/libpayload/arch/riscv/util.S new file mode 100644 index 0000000..dde2099 --- /dev/null +++ b/payloads/libpayload/arch/riscv/util.S @@ -0,0 +1,35 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2012 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +/* This function puts the system into a halt. */ +ENTRY(halt) + j halt +ENDPROC(halt) diff --git a/payloads/libpayload/arch/riscv/virtual.c b/payloads/libpayload/arch/riscv/virtual.c new file mode 100644 index 0000000..c3f4aa7 --- /dev/null +++ b/payloads/libpayload/arch/riscv/virtual.c @@ -0,0 +1,40 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> +#include <assert.h> +#include <die.h> +#include <stdlib.h> +#include <unistd.h> +#include <arch/cache.h> +#include <arch/virtual.h> +#include <arch/io.h> + +unsigned long virtual_offset = 0; +extern char _end[]; diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index b3ef342..2faf113 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -86,6 +86,12 @@ _ARCHEXTRA="" _ARCH=mips fi +if [ "$CONFIG_LP_ARCH_RISCV" = "y" ]; then + _ARCHINCDIR=$_INCDIR/riscv + _ARCHLIBDIR=$_LIBDIR/riscv + _ARCHEXTRA="" + _ARCH=riscv +fi if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHINCDIR=$_INCDIR/x86 _ARCHLIBDIR=$_LIBDIR/x86 diff --git a/payloads/libpayload/configs/config.riscv b/payloads/libpayload/configs/config.riscv new file mode 100644 index 0000000..7982b4a --- /dev/null +++ b/payloads/libpayload/configs/config.riscv @@ -0,0 +1,81 @@ +# +# Automatically generated file; DO NOT EDIT. +# Libpayload Configuration +# + +# +# Generic Options +# +# CONFIG_LP_GPL is not set +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_DEVELOPER is not set +# CONFIG_LP_CHROMEOS is not set +CONFIG_LP_COMPILER_GCC=y +# CONFIG_LP_COMPILER_LLVM_CLANG is not set +# CONFIG_LP_MEMMAP_RAM_ONLY is not set + +# +# Architecture Options +# +# CONFIG_LP_ARCH_ARM is not set +# CONFIG_LP_ARCH_X86 is not set +# CONFIG_LP_ARCH_ARM64 is not set +# CONFIG_LP_ARCH_MIPS is not set +CONFIG_LP_ARCH_RISCV=y +CONFIG_LP_HEAP_SIZE=131072 +CONFIG_LP_STACK_SIZE=16384 +CONFIG_LP_BASE_ADDRESS=0x80100000 + +# +# Standard Libraries +# +CONFIG_LP_LIBC=y +# CONFIG_LP_CURSES is not set +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y +CONFIG_LP_LZ4=y + +# +# Console Options +# +# CONFIG_LP_SKIP_CONSOLE_INIT is not set +CONFIG_LP_CBMEM_CONSOLE=y +# CONFIG_LP_SERIAL_CONSOLE is not set +CONFIG_LP_VIDEO_CONSOLE=y +# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set +# CONFIG_LP_PC_I8042 is not set +# CONFIG_LP_PC_MOUSE is not set +# CONFIG_LP_PC_KEYBOARD is not set + +# +# Drivers +# +# CONFIG_LP_MOUSE_CURSOR is not set +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +CONFIG_LP_TIMER_NONE=y +# CONFIG_LP_TIMER_MCT is not set +# CONFIG_LP_TIMER_TEGRA_1US is not set +# CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_ARMADA38X is not set +# CONFIG_LP_TIMER_IPQ40XX is not set +# CONFIG_LP_TIMER_ARM64_ARCH is not set +# CONFIG_LP_TIMER_RK3288 is not set +# CONFIG_LP_TIMER_RK3399 is not set +# CONFIG_LP_TIMER_CYGNUS is not set +# CONFIG_LP_TIMER_IMG_PISTACHIO is not set +# CONFIG_LP_TIMER_MTK is not set +# CONFIG_LP_TIMER_MVMAP2315 is not set +CONFIG_LP_TIMER_GENERIC_HZ=100000 +CONFIG_LP_TIMER_GENERIC_REG=0x0 +CONFIG_LP_TIMER_GENERIC_HIGH_REG=0x0 +CONFIG_LP_STORAGE=y +# CONFIG_LP_STORAGE_64BIT_LBA is not set +CONFIG_LP_STORAGE_ATA=y +CONFIG_LP_STORAGE_ATAPI=y +# CONFIG_LP_USB is not set +# CONFIG_LP_USB_GEN_HUB is not set +# CONFIG_LP_UDC is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +# CONFIG_LP_IO_ADDRESS_SPACE is not set +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/defconfig-riscv b/payloads/libpayload/configs/defconfig-riscv new file mode 100644 index 0000000..2ce2bc5 --- /dev/null +++ b/payloads/libpayload/configs/defconfig-riscv @@ -0,0 +1,3 @@ +CONFIG_LP_ARCH_RISCV=y +CONFIG_LP_TINYCURSES=n +CONFIG_LP_USB=n diff --git a/payloads/libpayload/include/riscv/arch/asm.h b/payloads/libpayload/include/riscv/arch/asm.h new file mode 100644 index 0000000..842fb0d --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/asm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + */ + +#ifndef __RISCV_ASM_H +#define __RISCV_ASM_H + +# define RISCV(x...) x +# define W(instr) instr + +#define ALIGN .align 2 + +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + +#define ENTRY(name) \ + .section .text.name, "ax", %progbits; \ + .global name; \ + ALIGN; \ + name: + +#define END(name) \ + .size name, .-name + +#endif /* __RISCV_ASM_H */ diff --git a/payloads/libpayload/include/riscv/arch/barrier.h b/payloads/libpayload/include/riscv/arch/barrier.h new file mode 100644 index 0000000..0b55df6 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/barrier.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +#include <arch/cache.h> + +/* + * Description of different memory barriers introduced: + * + * Memory barrier(mb) - Guarantees that all memory accesses specified before the + * barrier will happen before all memory accesses specified after the barrier + * + * Read memory barrier (rmb) - Guarantees that all read memory accesses + * specified before the barrier will happen before all read memory accesses + * specified after the barrier + * + * Write memory barrier (wmb) - Guarantees that all write memory accesses + * specified before the barrier will happen before all write memory accesses + * specified after the barrier + */ + +#define mb() +#define rmb() +#define wmb() + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/payloads/libpayload/include/riscv/arch/cache.h b/payloads/libpayload/include/riscv/arch/cache.h new file mode 100644 index 0000000..820bee9 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/cache.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.h: Cache maintenance API for RISCV + */ + +#ifndef RISCV_CACHE_H +#define RISCV_CACHE_H + +#include <stddef.h> +#include <stdint.h> + +/* + * Cache maintenance API + */ + +/* dcache clean and invalidate all (on current level given by CCSELR) */ +void dcache_clean_invalidate_all(void); + +/* dcache clean by virtual address to PoC */ +void dcache_clean_by_mva(void const *addr, size_t len); + +/* dcache clean and invalidate by virtual address to PoC */ +void dcache_clean_invalidate_by_mva(void const *addr, size_t len); + +/* dcache invalidate by virtual address to PoC */ +void dcache_invalidate_by_mva(void const *addr, size_t len); + +void dcache_clean_all(void); + +/* dcache invalidate all (on current level given by CCSELR) */ +void dcache_invalidate_all(void); + +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); + +/* Ensure that loaded program segment is synced back from cache to PoC */ +void arch_program_segment_loaded(void const *addr, size_t len); + +/* tlb invalidate all */ +void tlb_invalidate_all(void); + +/* Invalidate all of the instruction cache for PE to PoU. */ +static inline void icache_invalidate_all(void) +{ + return; +} + +#endif /* RISCV_CACHE_H */ diff --git a/payloads/libpayload/include/riscv/arch/io.h b/payloads/libpayload/include/riscv/arch/io.h new file mode 100644 index 0000000..8413b61 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/io.h @@ -0,0 +1,106 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_IO_H +#define _ARCH_IO_H + +#include <stdint.h> +#include <arch/cache.h> +//#include <arch/lib_helpers.h> + +/* + * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 + * instead for future development. + * + * TODO: make the existing code use read8/16/32 and write8/16/32 then remove + * readb/w/l and writeb/w/l. + */ + +static inline uint8_t readb(volatile const void *_a) +{ + return *(volatile const uint8_t *)_a; +} + +static inline uint16_t readw(volatile const void *_a) +{ + return *(volatile const uint16_t *)_a; +} + +static inline uint32_t readl(volatile const void *_a) +{ + return *(volatile const uint32_t *)_a; +} + +static inline void writeb(uint8_t _v, volatile void *_a) +{ + *(volatile uint8_t *)_a = _v; +} + +static inline void writew(uint16_t _v, volatile void *_a) +{ + *(volatile uint16_t *)_a = _v; +} + +static inline void writel(uint32_t _v, volatile void *_a) +{ + *(volatile uint32_t *)_a = _v; +} + +static inline uint8_t read8(const void *addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(const void *addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(const void *addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void write8(void *addr, uint8_t val) +{ + *(volatile uint8_t *)addr = val; +} + +static inline void write16(void *addr, uint16_t val) +{ + *(volatile uint16_t *)addr = val; +} + +static inline void write32(void *addr, uint32_t val) +{ + *(volatile uint32_t *)addr = val; +} + +#endif diff --git a/payloads/libpayload/include/riscv/arch/types.h b/payloads/libpayload/include/riscv/arch/types.h new file mode 100644 index 0000000..1bd815b --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/types.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2007 Uwe Hermann uwe@hermann-uwe.de + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_TYPES_H +#define _ARCH_TYPES_H + +typedef unsigned char uint8_t; +typedef unsigned char u8; +typedef signed char int8_t; +typedef signed char s8; + +typedef unsigned short uint16_t; +typedef unsigned short u16; +typedef signed short int16_t; +typedef signed short s16; + +typedef unsigned int uint32_t; +typedef unsigned int u32; +typedef signed int int32_t; +typedef signed int s32; + +typedef unsigned long long uint64_t; +typedef unsigned long long u64; +typedef signed long long int64_t; +typedef signed long long s64; + +typedef long time_t; +typedef long suseconds_t; + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#endif diff --git a/payloads/libpayload/include/riscv/arch/virtual.h b/payloads/libpayload/include/riscv/arch/virtual.h new file mode 100644 index 0000000..dac3480 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/virtual.h @@ -0,0 +1,41 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_VIRTUAL_H +#define _ARCH_VIRTUAL_H + +extern unsigned long virtual_offset; + +#define virt_to_phys(virt) ((unsigned long)(virt) + virtual_offset) +#define phys_to_virt(phys) ((void *)((unsigned long)(phys)-virtual_offset)) + +#define virt_to_bus(addr) virt_to_phys(addr) +#define bus_to_virt(addr) phys_to_virt(addr) + +#endif
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31356 )
Change subject: WIP: libpayload: add initial support for RISC-V ......................................................................
Patch Set 1:
(12 comments)
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... File payloads/libpayload/include/riscv/arch/asm.h:
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV)
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV)
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 24: name: labels should not be indented
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 27: .size name, .-name space required before that '-' (ctx:VxV)
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... File payloads/libpayload/include/riscv/arch/barrier.h:
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 57: #define mb() memory barrier without comment
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 58: #define rmb() memory barrier without comment
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 59: #define wmb() memory barrier without comment
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... File payloads/libpayload/include/riscv/arch/cache.h:
https://review.coreboot.org/#/c/31356/1/payloads/libpayload/include/riscv/ar... PS1, Line 81: } void function return statements are not generally useful
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31356
to look at the new patch set (#2).
Change subject: WIP: libpayload: add initial support for RISC-V ......................................................................
WIP: libpayload: add initial support for RISC-V
Parse fdt provided by a2 and extract coreboot tables from it.
Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Signed-off-by: Philipp Hug philipp@hug.cx --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c A payloads/libpayload/arch/riscv/sysinfo.c A payloads/libpayload/arch/riscv/timer.c A payloads/libpayload/arch/riscv/util.S A payloads/libpayload/arch/riscv/virtual.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.riscv A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h 20 files changed, 947 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31356/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31356 )
Change subject: WIP: libpayload: add initial support for RISC-V ......................................................................
Patch Set 2:
(8 comments)
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... File payloads/libpayload/include/riscv/arch/asm.h:
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV)
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV)
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 24: name: labels should not be indented
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/31356/2/payloads/libpayload/include/riscv/ar... PS2, Line 27: .size name, .-name space required before that '-' (ctx:VxV)
Attention is currently required from: Philipp Hug. Joey Madafferi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31356 )
Change subject: WIP: libpayload: add initial support for RISC-V ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2: ✅
Attention is currently required from: Philipp Hug. Martin Roth has removed Joey Madafferi from this change. ( https://review.coreboot.org/c/coreboot/+/31356 )
Change subject: WIP: libpayload: add initial support for RISC-V ......................................................................
Removed reviewer Joey Madafferi with the following votes:
* Code-Review+1 by Joey Madafferi joeymadafferi@gmail.com
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31356?usp=email )
Change subject: WIP: libpayload: add initial support for RISC-V ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
build bot (Jenkins) (Code Review) -
Joey Madafferi (Code Review)
-
Martin L Roth (Code Review)
-
Martin Roth (Code Review)
-
Philipp Hug (Code Review)