Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32070
Change subject: mb/*/romstage: Drop defines already set by raminit code ......................................................................
mb/*/romstage: Drop defines already set by raminit code
Drop defines that are set by raminit code.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c 19 files changed, 0 insertions(+), 265 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/1
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index a917722..68ed658 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -74,20 +74,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, .dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */ diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c19..6417f0d 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -71,20 +71,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, // 0 = leave channel enabled diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d34b1e4..cbd9f3d 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -132,20 +132,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66a503d0..6617dc4 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -127,20 +127,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .ddr3lv_support = 1, diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 76a4b4b..d76d814 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -101,20 +101,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 25f8d27..2244119 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -109,20 +109,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1..35345d0 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -106,20 +106,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index e47edc7..a5de6c0 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -124,20 +124,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 3125efe..5a8c972 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -111,20 +111,7 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 7539dd7..6e32145 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -137,20 +137,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 24ec912..2043cf6 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -29,20 +29,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9a9fc24..8cd7ec2 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -94,20 +94,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index f778f96..e0f8954 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -80,20 +80,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index a5b0c81..d398d81 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -50,20 +50,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa2,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index 685e942..df679f1 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -37,20 +37,6 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c index 97d9d2b..56ac32c 100644 --- a/src/mainboard/roda/rv11/variants/rw11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c @@ -66,20 +66,6 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 1080689..29fe08b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -156,20 +156,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a8e28d6..510efbe 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -144,20 +144,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 84ad047..702e8bb 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -66,20 +66,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, .ec_present = 0, .ddr_refresh_2x = 1,
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: mb/*/romstage: Drop defines already set by raminit code ......................................................................
Patch Set 4:
(3 comments)
I'd squash this with the previous patch
https://review.coreboot.org/#/c/32070/4/src/mainboard/asrock/h81m-hds/romsta... File src/mainboard/asrock/h81m-hds/romstage.c:
https://review.coreboot.org/#/c/32070/4/src/mainboard/asrock/h81m-hds/romsta... PS4, Line 77: : : : : : : : : : : : : : : not a sandy-bridge board, but haswell could benefit from the same changes ofc.
https://review.coreboot.org/#/c/32070/4/src/mainboard/google/slippy/variants... File src/mainboard/google/slippy/variants/falco/romstage.c:
https://review.coreboot.org/#/c/32070/4/src/mainboard/google/slippy/variants... PS4, Line 112: all these variants are haswell.
https://review.coreboot.org/#/c/32070/4/src/mainboard/supermicro/x10slm-f/ro... File src/mainboard/supermicro/x10slm-f/romstage.c:
https://review.coreboot.org/#/c/32070/4/src/mainboard/supermicro/x10slm-f/ro... PS4, Line 79: also a haswell board.
Hello Alexander Couzens, Patrick Rudolph, Tristan Corrick, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32070
to look at the new patch set (#5).
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
[WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb
* Move board specific settings to devicetree.cb * Don't overwrite pei structure in mainboard directory any more
Untested.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/stout/romstage.c M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/dcp847ske/usb.h M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/romstage.c 24 files changed, 353 insertions(+), 524 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/5
Hello Alexander Couzens, Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32070
to look at the new patch set (#8).
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
[WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb
* Move board specific settings to devicetree.cb * Don't overwrite pei structure in mainboard directory any more
Untested.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/stout/romstage.c M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/dcp847ske/usb.h M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/romstage.c 24 files changed, 352 insertions(+), 524 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/8
Hello Patrick Rudolph, Nico Rikken, Nathaniel Roach, Tristan Corrick, Duncan Laurie, build bot (Jenkins), Jan Tatje, Evgeny Zinoviev, Alexander Couzens, Felix Held, Bill XIE, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32070
to look at the new patch set (#9).
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
[WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb
* Move board specific settings to devicetree.cb * Don't overwrite pei structure in mainboard directory any more
Untested.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/stout/romstage.c A src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/dcp847ske/usb.h M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/kontron/ktqm77/romstage.c A src/mainboard/lenovo/t520/devicetree.cb A src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/romstage.c 27 files changed, 894 insertions(+), 524 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/9
Hello Patrick Rudolph, Nico Rikken, Nathaniel Roach, Tristan Corrick, Duncan Laurie, build bot (Jenkins), Jan Tatje, Evgeny Zinoviev, Alexander Couzens, Felix Held, Bill XIE, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32070
to look at the new patch set (#10).
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
[WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb
* Move board specific settings to devicetree.cb * Don't overwrite pei structure in mainboard directory any more
Untested.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/stout/romstage.c M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/dcp847ske/usb.h M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/romstage.c 24 files changed, 313 insertions(+), 524 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/10
Hello Patrick Rudolph, Nico Rikken, Nathaniel Roach, Tristan Corrick, Duncan Laurie, build bot (Jenkins), Jan Tatje, Evgeny Zinoviev, Alexander Couzens, Felix Held, Bill XIE, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32070
to look at the new patch set (#11).
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
[WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb
* Move board specific settings to devicetree.cb * Don't overwrite pei structure in mainboard directory any more
Untested.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/stout/romstage.c M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/dcp847ske/usb.h M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/romstage.c 24 files changed, 313 insertions(+), 524 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Patch Set 11:
(5 comments)
I like the idea. However, I would consider unifying both the native and mrc bootpaths' settings. Ideally, I would want that any sandy/ivy board could use either bootpath without requiring extra code.
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... File src/mainboard/google/butterfly/devicetree.cb:
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 23: register "spd_addresses" = "{ 0xA0, 0x00,0xA4,0x00 }" Could this be reused with the native raminit?
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 27: Do we need this many tabs?
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 29: register "usb_port_config" = "{ : /* enabled usb oc pin length */ : { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ : { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ : { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ : { 0, 0, 0x0000 }, /* P3: Empty */ : { 0, 0, 0x0000 }, /* P4: Empty */ : { 0, 0, 0x0000 }, /* P5: Empty */ : { 0, 0, 0x0000 }, /* P6: Empty */ : { 0, 0, 0x0000 }, /* P7: Empty */ : { 0, 4, 0x0000 }, /* P8: Empty */ : { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ : { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ : { 0, 4, 0x0000 }, /* P11: Empty */ : { 0, 4, 0x0000 }, /* P12: Empty */ : { 0, 4, 0x0000 }, /* P13: Empty */ : }" Couldn't this be generated from the native USB port settings? Two thirds of these values are exactly the same.
https://review.coreboot.org/#/c/32070/11/src/mainboard/intel/dcp847ske/usb.h File src/mainboard/intel/dcp847ske/usb.h:
PS11: This file is an attempt to unify USB configs. While it looks like a hack to me and should be replaced, it is interesting because it defines how to unify the USB settings for both the native and mrc bootpaths
https://review.coreboot.org/#/c/32070/11/src/mainboard/lenovo/x220/devicetre... File src/mainboard/lenovo/x220/devicetree.cb:
https://review.coreboot.org/#/c/32070/11/src/mainboard/lenovo/x220/devicetre... PS11, Line 27: register "usb_port_config" = "{ I'd say some USB port configs are missing here. Plus, this file is shared between the x220 and x1 variants.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Patch Set 11:
(4 comments)
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... File src/mainboard/google/butterfly/devicetree.cb:
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 23: register "spd_addresses" = "{ 0xA0, 0x00,0xA4,0x00 }"
Could this be reused with the native raminit?
Yes
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 27:
Do we need this many tabs?
probably not
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 29: register "usb_port_config" = "{ : /* enabled usb oc pin length */ : { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ : { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ : { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ : { 0, 0, 0x0000 }, /* P3: Empty */ : { 0, 0, 0x0000 }, /* P4: Empty */ : { 0, 0, 0x0000 }, /* P5: Empty */ : { 0, 0, 0x0000 }, /* P6: Empty */ : { 0, 0, 0x0000 }, /* P7: Empty */ : { 0, 4, 0x0000 }, /* P8: Empty */ : { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ : { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ : { 0, 4, 0x0000 }, /* P11: Empty */ : { 0, 4, 0x0000 }, /* P12: Empty */ : { 0, 4, 0x0000 }, /* P13: Empty */ : }"
Couldn't this be generated from the native USB port settings? Two thirds of these values are exactly […]
no. the future plan is to remove all native USB port settings and only use deviceteee values.
https://review.coreboot.org/#/c/32070/11/src/mainboard/intel/dcp847ske/usb.h File src/mainboard/intel/dcp847ske/usb.h:
PS11:
This file is an attempt to unify USB configs. […]
the idea is to have only devicetree settings
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Patch Set 11: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... File src/mainboard/google/butterfly/devicetree.cb:
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 29: register "usb_port_config" = "{ : /* enabled usb oc pin length */ : { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ : { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ : { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ : { 0, 0, 0x0000 }, /* P3: Empty */ : { 0, 0, 0x0000 }, /* P4: Empty */ : { 0, 0, 0x0000 }, /* P5: Empty */ : { 0, 0, 0x0000 }, /* P6: Empty */ : { 0, 0, 0x0000 }, /* P7: Empty */ : { 0, 4, 0x0000 }, /* P8: Empty */ : { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ : { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ : { 0, 4, 0x0000 }, /* P11: Empty */ : { 0, 4, 0x0000 }, /* P12: Empty */ : { 0, 4, 0x0000 }, /* P13: Empty */ : }"
no. the future plan is to remove all native USB port settings and only use deviceteee values.
Sure, the idea is to avoid deduplication.
https://review.coreboot.org/#/c/32070/11/src/mainboard/intel/dcp847ske/usb.h File src/mainboard/intel/dcp847ske/usb.h:
PS11:
the idea is to have only devicetree settings
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... File src/mainboard/google/butterfly/devicetree.cb:
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 29: register "usb_port_config" = "{ : /* enabled usb oc pin length */ : { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ : { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ : { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ : { 0, 0, 0x0000 }, /* P3: Empty */ : { 0, 0, 0x0000 }, /* P4: Empty */ : { 0, 0, 0x0000 }, /* P5: Empty */ : { 0, 0, 0x0000 }, /* P6: Empty */ : { 0, 0, 0x0000 }, /* P7: Empty */ : { 0, 4, 0x0000 }, /* P8: Empty */ : { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ : { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ : { 0, 4, 0x0000 }, /* P11: Empty */ : { 0, 4, 0x0000 }, /* P12: Empty */ : { 0, 4, 0x0000 }, /* P13: Empty */ : }"
Sure, the idea is to avoid deduplication.
oops, double negative. the idea is to avoid *duplication ._.
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Removed Code-Review+1 by Angel Pons th3fanbus@gmail.com
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/32070/11/src/mainboard/google/butte... File src/mainboard/google/butterfly/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32070/11/src/mainboard/google/butte... PS11, Line 27: register "max_mem_clock_mhz" = "800" # DDR3-1600 Looks like this was changed from DDR3-1333 to DDR3-1600
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32070?usp=email )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Martin L Roth (Code Review)
-
Patrick Rudolph (Code Review)