Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: [DO NOT MERGE] q1900m ......................................................................
[DO NOT MERGE] q1900m
Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/dptf.asl A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/mainboard.c A src/mainboard/asrock/q1900m/romstage.c A src/mainboard/asrock/q1900m/spd/spd0.spd.hex A src/mainboard/asrock/q1900m/spd/spd1.spd.hex 18 files changed, 841 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/1
diff --git a/src/mainboard/asrock/q1900m/Kconfig b/src/mainboard/asrock/q1900m/Kconfig new file mode 100644 index 0000000..79db93c --- /dev/null +++ b/src/mainboard/asrock/q1900m/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +if BOARD_ASROCK_Q1900M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select MAINBOARD_HAS_CHROMEOS + +config MAINBOARD_DIR + string + default "asrock/q1900m" + +config MAINBOARD_PART_NUMBER + string + default "Q1900M" + +config VGA_BIOS_FILE + string + default "pci8086,0f31.rom" + +endif diff --git a/src/mainboard/asrock/q1900m/Kconfig.name b/src/mainboard/asrock/q1900m/Kconfig.name new file mode 100644 index 0000000..1056ef9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_Q1900M + bool "Q1900M" diff --git a/src/mainboard/asrock/q1900m/Makefile.inc b/src/mainboard/asrock/q1900m/Makefile.inc new file mode 100644 index 0000000..8947e78 --- /dev/null +++ b/src/mainboard/asrock/q1900m/Makefile.inc @@ -0,0 +1,24 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = spd0 +SPD_SOURCES += spd1 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd + +ramstage-y += irqroute.c +ramstage-y += gpio.c diff --git a/src/mainboard/asrock/q1900m/acpi/dptf.asl b/src/mainboard/asrock/q1900m/acpi/dptf.asl new file mode 100644 index 0000000..bdc396b --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/dptf.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 80 + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.DPTF.TCPU, _SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { _SB.DPTF.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { _SB.DPTF.TCPU, _SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { _SB.DPTF.TCPU, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, // Revision + Package () { // Power Limit 1 + 0, // PowerLimitIndex, 0 for Power Limit 1 + 1600, // PowerLimitMinimum + 6200, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 200 // StepSize + }, + Package () { // Power Limit 2 + 1, // PowerLimitIndex, 1 for Power Limit 2 + 8000, // PowerLimitMinimum + 8000, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 1000 // StepSize + } +}) + +/* Include SoC DPTF */ +#include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asrock/q1900m/acpi/ec.asl b/src/mainboard/asrock/q1900m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/ec.asl diff --git a/src/mainboard/asrock/q1900m/acpi/superio.asl b/src/mainboard/asrock/q1900m/acpi/superio.asl new file mode 100644 index 0000000..e224349 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi/superio.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/q1900m/acpi_tables.c b/src/mainboard/asrock/q1900m/acpi_tables.c new file mode 100644 index 0000000..c8a95c6 --- /dev/null +++ b/src/mainboard/asrock/q1900m/acpi_tables.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <types.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/iomap.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/asrock/q1900m/board_info.txt b/src/mainboard/asrock/q1900m/board_info.txt new file mode 100644 index 0000000..d3e1fc2 --- /dev/null +++ b/src/mainboard/asrock/q1900m/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Q1900M/ +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: possible +Flashrom support: y diff --git a/src/mainboard/asrock/q1900m/devicetree.cb b/src/mainboard/asrock/q1900m/devicetree.cb new file mode 100644 index 0000000..3085696 --- /dev/null +++ b/src/mainboard/asrock/q1900m/devicetree.cb @@ -0,0 +1,118 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "1" + register "ide_legacy_combined" = "0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0" + register "usb3_port_disable_mask" = "0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuning for Q1900M board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + #register "gpu_pipea_port_select" = "2" # DP_C + #register "gpu_pipea_power_cycle_delay" = "6" # 600ms + #register "gpu_pipea_power_on_delay" = "5000" # 500ms + #register "gpu_pipea_light_on_delay" = "70" # 7ms + #register "gpu_pipea_power_off_delay" = "500" # 50ms + #register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on # LPC Bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 off # Keyboard + #io 0x60 = 0x60 + #io 0x62 = 0x64 + #irq 0x70 = 1 + #irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe3 = 0x14 + irq 0xe6 = 0x4c + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-Pull or Open-drain + device pnp 2e.14 off end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/asrock/q1900m/dsdt.asl b/src/mainboard/asrock/q1900m/dsdt.asl new file mode 100644 index 0000000..2e9de53 --- /dev/null +++ b/src/mainboard/asrock/q1900m/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/baytrail/acpi/platform.asl> + #include <soc/intel/baytrail/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + + /* Dynamic Platform Thermal Framework */ + //#include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asrock/q1900m/fadt.c b/src/mainboard/asrock/q1900m/fadt.c new file mode 100644 index 0000000..d07d157 --- /dev/null +++ b/src/mainboard/asrock/q1900m/fadt.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <string.h> +#include <soc/acpi.h> +#include <version.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = get_acpi_table_revision(FADT); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->reserved = 0; + fadt->preferred_pm_profile = PM_DESKTOP; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/asrock/q1900m/gpio.c b/src/mainboard/asrock/q1900m/gpio.c new file mode 100644 index 0000000..c1dfef9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/gpio.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * Note that Pad Number differs from GPIO Number. The pads list is in the BWG Vol2 Rev1p0. + * Chapter 35: GPIO Handling + * Table 35-2: Pad Number Mapping According to Pad Name + */ + + #define GPIO_INNC GPIO_INPUT_NOPU + #define GPIO_FS GPIO_INPUT_NOPU + +/* DDI0 = HDMI; DDI1 = DVI; no backlight used on either pipe */ + +/* NCORE GPIOs */ /* Map [15..26] to MCSI_GPIO[00..11] */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* [00] - HDMI DDC Detect */ // DDI0_HPD + GPIO_FUNC2, /* [01] - HDMI DDC Data */ // DDI0_DDCDATA + GPIO_FUNC2, /* [02] - HDMI DDC Clock */ // DDI0_DDCCLK + GPIO_INNC, /* [03] - No Connect */ // DDI0_VDDEN + GPIO_INNC, /* [04] - No Connect */ // DDI0_BKLTEN + GPIO_INNC, /* [05] - No Connect */ // DDI0_BKLTCTL + GPIO_FUNC2, /* [06] - DVI DDC Detect */ // DDI1_HPD + GPIO_FUNC2, /* [07] - DVI DDC Data */ // DDI1_DDCDATA + GPIO_FUNC2, /* [08] - DVI DDC Clock */ // DDI1_DDCCLK + GPIO_INNC, /* [09] - No Connect */ // DDI1_VDDEN + GPIO_INNC, /* [10] - No Connect */ // DDI1_BKLTEN + GPIO_INNC, /* [11] - No Connect */ // DDI1_BKLTCTL + GPIO_INNC, /* [12] - No Connect */ // RESERVED + GPIO_FS, /* [13] - No Connect */ // RESERVED (removed in EDS_Rev1p5) + GPIO_INNC, /* [14] - No Connect */ // RESERVED + GPIO_INNC, /* [15] - No Connect */ // OBSFN_C0 (XDP stuff) + GPIO_INNC, /* [16] - No Connect */ // XDP stuff + GPIO_INNC, /* [17] - No Connect */ // XDP stuff + GPIO_INNC, /* [18] - No Connect */ // XDP stuff + GPIO_INNC, /* [19] - No Connect */ // XDP stuff + GPIO_INNC, /* [20] - No Connect */ // XDP stuff + GPIO_INNC, /* [21] - No Connect */ // XDP stuff + GPIO_INNC, /* [22] - No Connect */ // XDP stuff + GPIO_INNC, /* [23] - No Connect */ // XDP stuff + GPIO_INNC, /* [24] - No Connect */ // Still camera 0 reset + GPIO_INNC, /* [25] - No Connect */ // Still camera 1 reset + GPIO_INNC, /* [26] - No Connect */ // Video camera reset + GPIO_END +}; + +/* SCORE GPIOs (_XX) */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FS, /* [000] - SATA_GP0 */ // SHOULD BE A PULL-UP, BUT READS LOW! + GPIO_FS, /* [001] - SATA_GP1 */ // EXTERNAL PULL UP + GPIO_FUNC1, /* [002] - SATA_LED_B */ // HDD LED + GPIO_FUNC1, /* [003] - PCIE_CLKREQ_0 */ // CLKREQ# FOR TOP PCIE X1 + GPIO_FUNC1, /* [004] - PCIE_CLKREQ_1 */ // CLKREQ# FOR PCIE X4 + GPIO_FUNC1, /* [005] - PCIE_CLKREQ_2 */ // CLKREQ# FOR BOTTOM PCIE X1 + GPIO_FUNC1, /* [006] - PCIE_CLKREQ_3 */ // CLKREQ# FOR LAN + GPIO_INNC, /* [007] - SD3_WP */ // NO CONNECT + GPIO_FUNC2, /* [008] - No Connect */ // HDA RESET + GPIO_FUNC2, /* [009] - No Connect */ // HDA SYNC + GPIO_FUNC2, /* [010] - No Connect */ // HDA CLK + GPIO_FUNC2, /* [011] - No Connect */ // HDA SDO + GPIO_FUNC2, /* [012] - No Connect */ // HDA SDI0 + GPIO_INNC, /* [013] - No Connect */ // NO CONNECT + GPIO_FS, /* [014] - No Connect */ // OTE_GATE1 !!! + GPIO_FS, /* [015] - No Connect */ // OTE_GATE2 !!! + GPIO_INNC, /* [016] - No Connect */ // NO CONNECT + GPIO_INNC, /* [017] - No Connect */ // NO CONNECT + GPIO_INNC, /* [018] - No Connect */ // NO CONNECT + GPIO_INNC, /* [019] - No Connect */ // NO CONNECT + GPIO_INNC, /* [020] - No Connect */ // NO CONNECT + GPIO_INNC, /* [021] - No Connect */ // NO CONNECT + GPIO_INNC, /* [022] - No Connect */ // NO CONNECT + GPIO_INNC, /* [023] - No Connect */ // NO CONNECT + GPIO_INNC, /* [024] - No Connect */ // NO CONNECT + GPIO_INNC, /* [025] - No Connect */ // NO CONNECT + GPIO_INNC, /* [026] - No Connect */ // NO CONNECT + GPIO_INNC, /* [027] - No Connect */ // NO CONNECT + GPIO_INNC, /* [028] - No Connect */ // NO CONNECT + GPIO_INNC, /* [029] - No Connect */ // NO CONNECT + GPIO_INNC, /* [030] - No Connect */ // NO CONNECT + GPIO_INNC, /* [031] - No Connect */ // NO CONNECT + GPIO_INNC, /* [032] - No Connect */ // NO CONNECT + GPIO_INNC, /* [033] - SD3_CLK */ // NO CONNECT + GPIO_INNC, /* [034] - SD3_D0 */ // NO CONNECT + GPIO_INNC, /* [035] - SD3_D1 */ // NO CONNECT + GPIO_INNC, /* [036] - SD3_D2 */ // NO CONNECT + GPIO_INNC, /* [037] - SD3_D3 */ // NO CONNECT + GPIO_INNC, /* [038] - SD3_CD# */ // NO CONNECT + GPIO_INNC, /* [039] - SD3_CMD */ // NO CONNECT + GPIO_INNC, /* [040] - No Connect */ // NO CONNECT + GPIO_INNC, /* [041] - SD3_PWREN */ // NO CONNECT + GPIO_FUNC1, /* [042] - No Connect */ // LAD0 + GPIO_FUNC1, /* [043] - No Connect */ // LAD1 + GPIO_FUNC1, /* [044] - No Connect */ // LAD2 + GPIO_FUNC1, /* [045] - No Connect */ // LAD3 + GPIO_FUNC1, /* [046] - No Connect */ // LFRAME# + GPIO_FUNC1, /* [047] - No Connect */ // LPC CLOCK (TPM) + GPIO_FUNC1, /* [048] - No Connect */ // LPC CLOCK (SIO) + GPIO_FUNC1, /* [049] - No Connect */ // LPC CLKRUN# + GPIO_FUNC1, /* [050] - No Connect */ // SERIRQ# + GPIO_FUNC1, /* [051] - PCU_SMB_DATA */ // SMBUS DATA + GPIO_FUNC1, /* [052] - PCU_SMB_CLK */ // SMBUS CLK + GPIO_FUNC1, /* [053] - PCU_SMB_ALERT */ // SMBUS ALERT# (UNUSED? STRAP?) + GPIO_FUNC1, /* [054] - ILB_8254_SPKR */ // SPEAKER + GPIO_FS, /* [055] - No Connect */ // FRONT PANEL PRESENCE (PIN 4) + GPIO_FS, /* [056] - _56 */ // TOP SWAP (DEFEATURE) + GPIO_INNC, /* [057] - PCU_UART3_TXD */ // NO CONNECT + GPIO_INNC, /* [058] - No Connect */ // NO CONNECT + GPIO_INNC, /* [059] - No Connect */ // NO CONNECT + GPIO_INNC, /* [060] - No Connect */ // NO CONNECT + GPIO_FS, /* [061] - PCU_UART3_RXD */ // PCIE3_SEL !!! + GPIO_INNC, /* [062] - LPE_I2S_CLK */ // NO CONNECT + GPIO_FS, /* [063] - LPE_I2S_FRM */ // BOOT SEL STRAP + GPIO_INNC, /* [064] - LPE_I2S_DATIN */ // NO CONNECT + GPIO_FS, /* [065] - LPE_I2S_DATOUT */ // IFD OVERRIDE STRAP + GPIO_INNC, /* [066] - SOC_SIO_SPI_CS1 */ // NO CONNECT + GPIO_INNC, /* [067] - SOC_SIO_SPI_MISO */ // NO CONNECT + GPIO_INNC, /* [068] - SOC_SIO_SPI_MOSI */ // NO CONNECT + GPIO_INNC, /* [069] - SOC_SIO_SPI_CLK */ // NO CONNECT + GPIO_INNC, /* [070] - SIO_UART1_RXD */ // NO CONNECT + GPIO_INNC, /* [071] - SIO_UART1_TXD */ // NO CONNECT + GPIO_INNC, /* [072] - No Connect */ // NO CONNECT + GPIO_INNC, /* [073] - No Connect */ // NO CONNECT + GPIO_INNC, /* [074] - No Connect */ // NO CONNECT + GPIO_INNC, /* [075] - No Connect */ // NO CONNECT + GPIO_INNC, /* [076] - No Connect */ // NO CONNECT + GPIO_INNC, /* [077] - No Connect */ // NO CONNECT + GPIO_INNC, /* [078] - No Connect */ // NO CONNECT + GPIO_INNC, /* [079] - No Connect */ // NO CONNECT + GPIO_INNC, /* [080] - No Connect */ // NO CONNECT + GPIO_INNC, /* [081] - No Connect */ // NO CONNECT + GPIO_INNC, /* [082] - No Connect */ // NO CONNECT + GPIO_INNC, /* [083] - No Connect */ // NO CONNECT + GPIO_INNC, /* [084] - No Connect */ // NO CONNECT + GPIO_INNC, /* [085] - No Connect */ // NO CONNECT + GPIO_INNC, /* [086] - No Connect */ // NO CONNECT + GPIO_INNC, /* [087] - No Connect */ // NO CONNECT + GPIO_INNC, /* [088] - No Connect */ // NO CONNECT + GPIO_INNC, /* [089] - No Connect */ // NO CONNECT + GPIO_INNC, /* [090] - EXP_I2C_SDA */ // NO CONNECT + GPIO_INNC, /* [091] - EXP_I2C_SCL */ // NO CONNECT + GPIO_FS, /* [092] - 0R GND? */ // PCIE1_SEL !!! + GPIO_FS, /* [093] - 0R GND? */ // PCIE2_SEL !!! + GPIO_INNC, /* [094] - SOC_PWM0 */ // NO CONNECT + GPIO_INNC, /* [095] - SOC_PWM1 */ // NO CONNECT + GPIO_FUNC1, /* [096] - No Connect */ // PMC PLT CLK0 + GPIO_FUNC1, /* [097] - No Connect */ // PMC PLT CLK1 + GPIO_INNC, /* [098] - No Connect */ // NO CONNECT + GPIO_INNC, /* [099] - No Connect */ // NO CONNECT + GPIO_INNC, /* [100] - No Connect */ // NO CONNECT + GPIO_INNC, /* [101] - No Connect */ // NO CONNECT + GPIO_END +}; + +/* SSUS GPIOs () */ +static const struct soc_gpio_map gp_ssus_gpio_map[] = { + GPIO_FS, /* [00] - No Connect */ // RINGIN# !!! + GPIO_INNC, /* [01] - PMC_WAKE_PCIE[1] */ // NO CONNECT + GPIO_INNC, /* [02] - PMC_WAKE_PCIE[2] */ // PME# (SIO) + GPIO_INNC, /* [03] - PMC_WAKE_PCIE[3] */ // SMI# (SIO) + GPIO_INNC, /* [04] - No Connect */ // NO CONNECT + GPIO_INNC, /* [05] - No Connect */ // NO CONNECT + GPIO_INNC, /* [06] - No Connect */ // NO CONNECT + GPIO_INNC, /* [07] - No Connect */ // NO CONNECT + GPIO_INNC, /* [08] - No Connect */ // NO CONNECT + GPIO_INNC, /* [09] - No Connect */ // NO CONNECT + GPIO_INNC, /* [10] - _10_UNLOCK */ // NO CONNECT + GPIO_FUNC0, /* [11] - SUSPWRDNACK */ // SUSPWRDNACK + GPIO_FS, /* [12] - No Connect */ // NO CONNECT ??? + GPIO_INNC, /* [13] - No Connect */ // NO CONNECT + GPIO_INNC, /* [14] - 14_J20 */ // NO CONNECT + GPIO_FUNC0, /* [15] - PMC_WAKE_PCIE[0] */ // SOC PCIE WAKE# + GPIO_FUNC0, /* [16] - No Connect */ // POWER BUTTON (SIO) + GPIO_INNC, /* [17] - No Connect */ // NO CONNECT + GPIO_FUNC0, /* [18] - T360 */ // SUS STAT# + GPIO_FUNC0, /* [19] - SOC_USB_HOST_OC0 */ // USB OC0# + GPIO_FUNC0, /* [20] - SOC_USB_HOST_OC1 */ // USB OC1# + GPIO_INNC, /* [21] - SOC_SPI_CS1B */ // NO CONNECT + GPIO_OUT_LOW, /* [22] - No Connect */ // MEMORY VR VCCM OV1 !!! + GPIO_FS, /* [23] - No Connect */ // MEMORY VR VCCM OV2 !!! + GPIO_INNC, /* [24] - No Connect */ // NO CONNECT + GPIO_INNC, /* [25] - No Connect */ // NO CONNECT + GPIO_INNC, /* [26] - No Connect */ // NO CONNECT + GPIO_INNC, /* [27] - SW450-1 */ // MBREV0 + GPIO_INNC, /* [28] - SW450-2 */ // MBREV1 + GPIO_INNC, /* [29] - SW450-3 */ // MBREV2 + GPIO_INNC, /* [30] - SW450-4 */ // MBREV3 + GPIO_INNC, /* [31] - No Connect */ // NO CONNECT + GPIO_INNC, /* [32] - No Connect */ // NO CONNECT + GPIO_INNC, /* [33] - No Connect */ // NO CONNECT + GPIO_INNC, /* [34] - No Connect */ // NO CONNECT + GPIO_INNC, /* [35] - No Connect */ // NO CONNECT + GPIO_INNC, /* [36] - No Connect */ // NO CONNECT + GPIO_INNC, /* [37] - No Connect */ // NO CONNECT + GPIO_INNC, /* [38] - No Connect */ // NO CONNECT + GPIO_INNC, /* [39] - No Connect */ // NO CONNECT + GPIO_INNC, /* [40] - No Connect */ // NO CONNECT + GPIO_INNC, /* [41] - No Connect */ // NO CONNECT + GPIO_INNC, /* [42] - No Connect */ // NO CONNECT + GPIO_INNC, /* [43] - No Connect */ // NO CONNECT + GPIO_END +}; + +/* +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +};*/ + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gp_ssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, + //.core_dirq = &core_dedicated_irq, + //.sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/asrock/q1900m/irqroute.c b/src/mainboard/asrock/q1900m/irqroute.c new file mode 100644 index 0000000..df43ee9 --- /dev/null +++ b/src/mainboard/asrock/q1900m/irqroute.c @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/asrock/q1900m/irqroute.h b/src/mainboard/asrock/q1900m/irqroute.h new file mode 100644 index 0000000..3944c9de --- /dev/null +++ b/src/mainboard/asrock/q1900m/irqroute.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +//#define TPAD_IRQ_OFFSET 0 +//#define TOUCH_IRQ_OFFSET 1 +//#define I8042_IRQ_OFFSET 2 +//#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +//#define TPAD_IRQ_GPIO 55 +//#define TOUCH_IRQ_GPIO 72 +//#define I8042_IRQ_GPIO 101 +//#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +//#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +//#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/asrock/q1900m/mainboard.c b/src/mainboard/asrock/q1900m/mainboard.c new file mode 100644 index 0000000..09d807d --- /dev/null +++ b/src/mainboard/asrock/q1900m/mainboard.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG(VGA_ROM_RUN) +#include <x86emu/x86emu.h> +#endif +#include <arch/acpi.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <smbios.h> +//#include <variant/onboard.h> +#include <soc/gpio.h> +#include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +//static void mainboard_init(struct device *dev) {} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + //dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asrock/q1900m/romstage.c b/src/mainboard/asrock/q1900m/romstage.c new file mode 100644 index 0000000..7a4d5a6 --- /dev/null +++ b/src/mainboard/asrock/q1900m/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/mrc_wrapper.h> +#include <soc/romstage.h> + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* I'm a bit desperate. */ + printk(BIOS_EMERG, "AAAAAAAA WE LIVEEEEEEEEEE\n"); + void *spd; + size_t spd_fsize; + + struct mrc_params mp = { + .mainboard = { + .dram_type = DRAM_DDR3, + .dram_info_location = DRAM_INFO_SPD_MEM, + .weaker_odt_settings = 1, + .dram_is_slotted = 1, + .spd_addrs = {0xf0, 0x00} + }, + }; + + spd = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); + + if (!spd) + die("SPD data not found."); + + mp.mainboard.dram_data[0] = spd; + //mp.mainboard.dram_data[1] = spd; + + rp->mrc_params = ∓ + romstage_common(rp); +} diff --git a/src/mainboard/asrock/q1900m/spd/spd0.spd.hex b/src/mainboard/asrock/q1900m/spd/spd0.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/asrock/q1900m/spd/spd0.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/asrock/q1900m/spd/spd1.spd.hex b/src/mainboard/asrock/q1900m/spd/spd1.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/asrock/q1900m/spd/spd1.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: [DO NOT MERGE] q1900m ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... File src/mainboard/asrock/q1900m/fadt.c:
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... PS1, Line 8: void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) "foo * bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... PS1, Line 8: void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) "foo * bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... File src/mainboard/asrock/q1900m/gpio.c:
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... PS1, Line 229: struct soc_gpio_config* mainboard_get_gpios(void) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... File src/mainboard/asrock/q1900m/irqroute.h:
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... PS1, Line 8: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/39658/1/src/mainboard/asrock/q1900m... PS1, Line 24: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: [DO NOT MERGE] q1900m ......................................................................
Set Ready For Review
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: [WIP] mb/asrock/q1900m: Add new mainboard ......................................................................
Set Ready For Review
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: [WIP] mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 11:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39658/11/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/gpio.c:
https://review.coreboot.org/c/coreboot/+/39658/11/src/mainboard/asrock/q1900... PS11, Line 114: [55] = GPIO_FS, // BD12 - PF_PRES# (HDA FRONT PANEL PRESENCE - PIN 4) 'PRES' may be misspelled - perhaps 'PRESS'?
https://review.coreboot.org/c/coreboot/+/39658/11/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/irqroute.h:
https://review.coreboot.org/c/coreboot/+/39658/11/src/mainboard/asrock/q1900... PS11, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/39658/11/src/mainboard/asrock/q1900... PS11, Line 23: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39658
to look at the new patch set (#12).
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
mb/asrock/q1900m: Add new mainboard
This is a µATX mainboard with a Celeron J1900 and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI, DVI and VGA - Realtek GbE - Both SATA ports - RAM initialization with MRC binary - Flashing with flashrom - SeaBIOS and TianoCore to boot Arch Linux
Not working: - Something stalls the system for 30 seconds at boot.
Untested - VGA BIOS - PCIe ports - Audio - S3 suspend/resume - Front USB headers - PS/2 connectors - TPM header - Non-Linux OSes - Parallel port - IRQ routing
Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/data.vbt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gma-mainboard.ads A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/romstage.c 16 files changed, 567 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/12
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39658/12/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/irqroute.h:
https://review.coreboot.org/c/coreboot/+/39658/12/src/mainboard/asrock/q1900... PS12, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/39658/12/src/mainboard/asrock/q1900... PS12, Line 23: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39658
to look at the new patch set (#13).
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
mb/asrock/q1900m: Add new mainboard
This is a µATX mainboard with a Celeron J1900 and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI, DVI and VGA - Realtek GbE - Both SATA ports - RAM initialization with MRC binary - S3 suspend/resume - Flashing with flashrom - SeaBIOS and TianoCore to boot Arch Linux
Not working: - Something stalls the system for 30 seconds at boot.
Untested - VGA BIOS - PCIe ports - Audio - Front USB headers - PS/2 connectors - TPM header - Non-Linux OSes - Parallel port - IRQ routing
Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/data.vbt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gma-mainboard.ads A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/romstage.c 16 files changed, 567 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/13
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39658/13/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/romstage.c:
https://review.coreboot.org/c/coreboot/+/39658/13/src/mainboard/asrock/q1900... PS13, Line 43: mainboard_config_superio Do this in the bootblock?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39658/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39658/13//COMMIT_MSG@22 PS13, Line 22: - SeaBIOS and TianoCore to boot Arch Linux It’d be great if you added the used versions.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39658
to look at the new patch set (#14).
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
mb/asrock/q1900m: Add new mainboard
This is a µATX mainboard with a Celeron J1900 and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI, DVI and VGA - Realtek GbE - Rear audio connectors - Both SATA ports - RAM initialization with MRC binary - S3 suspend/resume - Flashing with flashrom - SeaBIOS and TianoCore to boot Arch Linux
Not working: - Something stalls the system for 30 seconds at boot.
Untested - VGA BIOS - PCIe ports - Front audio header - Front USB headers - PS/2 connectors - TPM header - Non-Linux OSes - Parallel port - IRQ routing
Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/bootblock.c A src/mainboard/asrock/q1900m/data.vbt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gma-mainboard.ads A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/romstage.c 17 files changed, 572 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/14
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39658
to look at the new patch set (#16).
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
mb/asrock/q1900m: Add new mainboard
This is a µATX mainboard with a Celeron J1900 and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI, DVI and VGA - Realtek GbE - Rear audio connectors - Both SATA ports - RAM initialization with MRC binary - S3 suspend/resume - Flashing with flashrom - SeaBIOS and TianoCore to boot Arch Linux
Not working: - Something stalls the system for 30 seconds at boot.
Untested - VGA BIOS - PCIe ports - Front audio header - Front USB headers - PS/2 connectors - TPM header - Non-Linux OSes - Parallel port - IRQ routing
Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/bootblock.c A src/mainboard/asrock/q1900m/data.vbt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gma-mainboard.ads A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/romstage.c 17 files changed, 570 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/16
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39658/13/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/romstage.c:
https://review.coreboot.org/c/coreboot/+/39658/13/src/mainboard/asrock/q1900... PS13, Line 43: mainboard_config_superio
Do this in the bootblock?
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 16:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/irqroute.h:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 7: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 23: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39658
to look at the new patch set (#17).
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
mb/asrock/q1900m: Add new mainboard
This is a µATX mainboard with a Celeron J1900 and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI, DVI and VGA - Realtek GbE - Rear audio connectors - Both SATA ports - RAM initialization with MRC binary - S3 suspend/resume - Flashing with flashrom - SeaBIOS 1.14.0 and TianoCore CorebootPayloadPkk payloads - Booting to Arch Linux on SATA SSD
Not working: - Something stalls the system for 30 seconds at boot.
Untested - VGA BIOS - PCIe ports - Front audio header - Front USB headers - PS/2 connectors - TPM header - Non-Linux OSes - Parallel port - IRQ routing
Change-Id: Id029074e4231db231a68bc92a4210dc052bba1c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asrock/q1900m/Kconfig A src/mainboard/asrock/q1900m/Kconfig.name A src/mainboard/asrock/q1900m/Makefile.inc A src/mainboard/asrock/q1900m/acpi/ec.asl A src/mainboard/asrock/q1900m/acpi/superio.asl A src/mainboard/asrock/q1900m/acpi_tables.c A src/mainboard/asrock/q1900m/board_info.txt A src/mainboard/asrock/q1900m/bootblock.c A src/mainboard/asrock/q1900m/data.vbt A src/mainboard/asrock/q1900m/devicetree.cb A src/mainboard/asrock/q1900m/dsdt.asl A src/mainboard/asrock/q1900m/fadt.c A src/mainboard/asrock/q1900m/gma-mainboard.ads A src/mainboard/asrock/q1900m/gpio.c A src/mainboard/asrock/q1900m/irqroute.c A src/mainboard/asrock/q1900m/irqroute.h A src/mainboard/asrock/q1900m/romstage.c 17 files changed, 570 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39658/17
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/fadt.c:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 7: acpi_create_fadt Please, why don't you use the one we already have here: src/acpi/acpi.c ?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 16:
(6 comments)
Looks pretty good. LGTM?
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 108: 4e.0 I might be wrong about this... This is usually set to 0c31.0 which IIRC is just a HID in ACPI an not an actual IO port because all IO happens via memory mapped operation at CONFIG_TPM_TIS_BASE_ADDRESS. So my question is if there is really something responding at IO 4e?
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/irqroute.h:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 10: PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ This is off in DT?
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 13: PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ : PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ : PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ : PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ off in DT?
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 20: PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ off in DT?
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/romstage.c:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 26: 0x03 Are there defines somewhere for this?
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 27: spd[1] spd[1] ends up unused?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 17:
(7 comments)
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 108: 4e.0
I might be wrong about this... This is usually set to 0c31. […]
Probably not, definitely not on TPM 2.0 stuff. I haven't tested this, but Asrock B85M Pro4 works just fine (even better than on vendor BIOS) with the same code and a TPM 2.0.
I could try using `device mmio 0xfed40000` instead (the actual device address).
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/fadt.c:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 7: acpi_create_fadt
Please, why don't you use the one we already have here: src/acpi/acpi. […]
Why does this even build in the first place? Wait, did anyone select HAVE_ACPI_TABLES somewhere?
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/irqroute.h:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 10: PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
This is off in DT?
Sure. I haven't checked these at all, so they are completely wrong.
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 13: PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ : PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ : PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ : PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
off in DT?
I want to enable TXE, but it doesn't respond and mei_txe shits a brick. The rest shall go away.
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/romstage.c:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 8: static uint8_t spd[2][256]; #define SPD_SIZE 256 static uint8_t spd[NUM_CHANNELS][SPD_SIZE];
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 26: 0x03
Are there defines somewhere for this?
probably in src/include/device/dram/ddr3.h
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 27: spd[1]
spd[1] ends up unused?
No, MRC will access this data even though the two dram_data pointers are the same. See the comment on line 32. It accesses the contents of spd[0] through dram_data[0] and the contents of spd[1] through dram_data[1].
I can change `spd[0]` to `spd` on lines 33 and 34, though.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/fadt.c:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 7: acpi_create_fadt
Why does this even build in the first place? Wait, did anyone select HAVE_ACPI_TABLES somewhere?
I've checked with 'make menuconfig' and 'HAVE_ACPI_TABLES [=y]' for your board
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39658 )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... File src/mainboard/asrock/q1900m/fadt.c:
https://review.coreboot.org/c/coreboot/+/39658/16/src/mainboard/asrock/q1900... PS16, Line 7: acpi_create_fadt
I've checked with 'make menuconfig' and 'HAVE_ACPI_TABLES [=y]' for your board
kidding 😂
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39658?usp=email )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
Angel Pons has restored this change. ( https://review.coreboot.org/c/coreboot/+/39658?usp=email )
Change subject: mb/asrock/q1900m: Add new mainboard ......................................................................
Restored
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
build bot (Jenkins) (Code Review)
-
HAOUAS Elyes (Code Review)
-
Martin L Roth (Code Review)
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Name of user not set (Code Review)
-
Paul Menzel (Code Review)