Looks pretty good. LGTM?
6 comments:
File src/mainboard/asrock/q1900m/devicetree.cb:
I might be wrong about this... This is usually set to 0c31.0 which IIRC is just a HID in ACPI an not an actual IO port because all IO happens via memory mapped operation at CONFIG_TPM_TIS_BASE_ADDRESS. So my question is if there is really something responding at IO 4e?
File src/mainboard/asrock/q1900m/irqroute.h:
Patch Set #16, Line 10: PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
This is off in DT?
PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
off in DT?
Patch Set #16, Line 20: PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
off in DT?
File src/mainboard/asrock/q1900m/romstage.c:
Are there defines somewhere for this?
Patch Set #16, Line 27: spd[1]
spd[1] ends up unused?
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