Change in coreboot[master]: postcodes: replaced postcode values with their respective defined con...
Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: postcodes: replaced postcode values with their respective defined constants ......................................................................
postcodes: replaced postcode values with their respective defined constants
- Replaced existing post_code() call values with the defined constants - Reorganized certain post_code calls to match their defines - Added few post_code() calls which were missing - Deleted certain duplicate post_code() calls
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/arch/x86/tables.c M src/cpu/intel/car/bootblock.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/bootblock.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/romstage.c 48 files changed, 160 insertions(+), 125 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/1
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index dcacc70..0a3698c 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -30,6 +30,8 @@
display_mtrrs();
+ post_code(POST_ENTRY_RAMSTAGE); /* Load and run ramstage. */ run_ramstage(); + post_code(POST_RAMSTAGE_DIE); } diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 084384e..146a3b6 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -97,12 +97,14 @@ void prepare_and_run_postcar(struct postcar_frame *pcf) { if (postcar_frame_init(pcf, 0)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n");
fill_postcar_frame(pcf);
postcar_frame_common_mtrrs(pcf);
+ post_code(POST_ENTRY_POST_CAR); run_postcar_phase(pcf); /* We do not return here. */ } diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 492674c..8783925 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -17,7 +17,7 @@ unsigned long high_table_pointer;
#define MAX_PIRQ_TABLE_SIZE (4 * 1024) - post_code(0x9a); + post_code(POST_TABLE_IRQ_WRITE);
/* This table must be between 0x0f0000 and 0x100000 */ rom_table_end = write_pirq_routing_table(rom_table_end); @@ -49,7 +49,7 @@ unsigned long high_table_pointer;
#define MAX_MP_TABLE_SIZE (4 * 1024) - post_code(0x9b); + post_code(POST_TABLE_MP_WRITE);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ rom_table_end = write_smp_table(rom_table_end); @@ -78,7 +78,7 @@ unsigned long high_table_pointer; const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB;
- post_code(0x9c); + post_code(POST_TABLE_ACPI_WRITE);
/* Write ACPI tables to F segment and high tables area */
diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index dd9a772..1070a9b 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <arch/bootblock.h> #include <cpu/x86/bist.h> +#include <console/console.h>
static uint32_t saved_bist;
@@ -22,6 +23,7 @@ bootblock_early_northbridge_init(); bootblock_early_southbridge_init(); bootblock_early_cpu_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); }
void bootblock_soc_init(void) diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..2983257 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -12,7 +12,7 @@ bootblock_pre_c_entry:
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
/* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -25,7 +25,7 @@ bt $12, %eax jc wait_for_sipi
- post_code(0x22) + post_code(POST_CAR_INIT_IPI)
/* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -38,6 +38,8 @@ wrmsr jnz clear_fixed_mtrr
+ post_code(POST_CAR_FIXED_MTRR) + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr @@ -54,7 +56,7 @@ dec %ebx jnz clear_var_mtrr
- post_code(0x22) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -79,7 +81,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -87,7 +88,7 @@ xorl %edx, %edx wrmsr
- post_code(0x24) + post_code(POST_CAR_BASE_ADDRESS) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -95,7 +96,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x25) + post_code(POST_CAR_MTRR_ENABLE)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -115,6 +116,7 @@ invd movl %eax, %cr0
+ post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -123,7 +125,7 @@ shr $2, %ecx rep stosl
- post_code(0x26) + post_code(POST_CAR_CACHE_EVICTION) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -142,12 +144,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x28) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp
@@ -165,7 +168,7 @@ pushl %eax /* tsc[31:0] */
before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d087365..94bfeaa 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -17,7 +17,7 @@ jmp check_mtrr /* Check if CPU properly reset */
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
/* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -30,14 +30,13 @@ bt $12, %eax jc wait_for_sipi
- post_code(0x21) + post_code(POST_CAR_INIT_IPI) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr
- post_code(0x22) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax @@ -49,6 +48,8 @@ wrmsr jnz clear_fixed_mtrr
+ post_code(POST_CAR_FIXED_MTRR) + /* Zero out all variable range MTRRs. */ movl $MTRR_CAP_MSR, %ecx rdmsr @@ -64,6 +65,7 @@ dec %edi jnz clear_var_mtrrs
+ post_code(POST_CAR_VARIABLE_MTRR) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $0x80000008, %eax cpuid @@ -84,7 +86,6 @@ wrmsr
- post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -92,7 +93,7 @@ xorl %edx, %edx wrmsr
- post_code(0x24) + post_code(POST_CAR_BASE_ADDRESS) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -113,7 +114,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x25) + post_code(POST_CAR_MTRR_ENABLE)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -170,6 +171,7 @@ andl $~2, %eax wrmsr
+ post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -178,13 +180,13 @@ shr $2, %ecx rep stosl
+ post_code(POST_CAR_CACHE_EVICTION) /* enable the 'no eviction run' state */ movl $NoEvictMod_MSR, %ecx rdmsr orl $3, %eax wrmsr
- post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -195,12 +197,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x28) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp
@@ -218,7 +221,7 @@ pushl %eax /* tsc[31:0] */
before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 2834e76..260b90e 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -12,14 +12,14 @@ chipset_teardown_car: pop %esp
- post_code(0x30) + post_code(POST_ENTRY_POST_CAR)
/* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0
- post_code(0x31) + post_code(POST_CAR_CACHE_EVICTION)
/* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e3447..8e5e6e7 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -12,7 +12,7 @@ bootblock_pre_c_entry:
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
/* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -24,6 +24,7 @@ movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR)
/* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -40,7 +41,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_CAR_VARIABLE_MTRR)
/* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -48,8 +49,6 @@ andl $(~0x00000cff), %eax wrmsr
- post_code(0x22) - /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax cpuid @@ -66,8 +65,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(0x2a) - /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -75,6 +72,8 @@ xorl %edx, %edx wrmsr
+ post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -82,7 +81,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x2b) + post_code(POST_CAR_MTRR_ENABLE)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -90,14 +89,13 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr
- post_code(0x2c) - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0
+ post_code(POST_CAR_CACHE_EVICTION) /* Read then clear the CAR region. This will also fill up the cache. * IMPORTANT: The read is mandatory. */ @@ -112,7 +110,6 @@ xorl %eax, %eax rep stosl
- post_code(0x2d) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -131,12 +128,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x2e) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp
@@ -154,7 +152,7 @@ pushl %eax /* tsc[31:0] */
before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e36538..74ff544 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -16,7 +16,7 @@ bootblock_pre_c_entry:
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
movl $LAPIC_BASE_MSR, %ecx rdmsr @@ -33,6 +33,7 @@ movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR)
/* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -49,7 +50,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_CAR_VARIABLE_MTRR)
/* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -57,8 +58,6 @@ andl $(~0x00000cff), %eax wrmsr
- post_code(0x22) - /* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. */ @@ -207,15 +206,14 @@
sipi_complete:
- post_code(0x2a) - /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr - + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -223,7 +221,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x2b) + post_code(POST_CAR_MTRR_ENABLE)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -293,7 +291,7 @@ jmp update_bsp_microcode end_microcode_update: #endif - post_code(0x2d) + post_code(POST_CAR_CACHE_EVICTION) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -333,13 +331,14 @@ wrmsr
fill_cache: - post_code(0x2e) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0
+ post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -348,6 +347,7 @@ shr $2, %ecx rep stosl
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp
@@ -365,7 +365,7 @@ pushl %eax /* tsc[31:0] */
before_c_entry: - post_code(0x2f) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 108342f..0dec603 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -10,7 +10,7 @@ chipset_teardown_car: pop %esp
- post_code(0x30) + post_code(POST_ENTRY_POST_CAR)
/* Disable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4b56301..04abdb2 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -19,7 +19,7 @@ int wake_from_s3;
enable_lapic(); - + post_code(POST_ENTRY_ROMSTAGE); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
/* Perform some early chipset initialization required @@ -56,10 +56,11 @@ params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data); + post_code(POST_ROM_SDRAM_INIT);
timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3b); + post_code(POST_RAM_INIT);
intel_early_me_status();
@@ -80,5 +81,5 @@
romstage_handoff_init(wake_from_s3);
- post_code(0x3f); + post_code(POST_ROM_STAGE_HANDOFF); } diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 1b46403e..3675e4a 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -6,11 +6,12 @@
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - post_code(0x05); + post_code(POST_ENTRY_C_BOOTBLOCK);
/* Halt if there was a built in self test failure */ if (bist) { console_init(); + post_code(POST_CONSOLE_READY); report_bist_failure(bist); }
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 30f9f9c..ebe5de1 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -6,12 +6,13 @@ bootblock_pre_c_entry:
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* * Nothing to do here on qemu, RAM works just fine without any * initialization. */
+ post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also clear CAR GLOBAL */ movl $_car_region_start, %edi movl $_car_region_end, %ecx @@ -20,7 +21,7 @@ xorl %eax, %eax rep stosl
- post_code(0x21) + post_code(POST_ENTRY_BOOTBLOCK_STACK)
movl $_ecar_stack, %esp
@@ -47,7 +48,7 @@ #endif
before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Never returns */ .Lhlt: diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 77525a7..f961f41 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -826,7 +826,7 @@
printk(BIOS_DEBUG, "\n");
- post_code(0x93); + post_code(POST_BOOTBLOCK_MTRR_CHECK); }
static bool put_back_original_solution; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 032e15c..0ecf86a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1237,7 +1237,7 @@ max_devfn=0xff; }
- post_code(0x24); + post_code(POST_PCI_SCAN_BUS);
/* * Probe all devices/functions on this bus with some optimization for @@ -1317,7 +1317,7 @@ * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ - post_code(0x55); + post_code(POST_PCI_SCAN_EXIT); }
typedef enum { diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29..8a39a2f 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,7 +27,7 @@ */ bootblock_pre_c_entry:
- post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
AMD_ENABLE_STACK
@@ -42,6 +42,7 @@ test $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax jz ap_entry
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) mov $_ecar_stack, %esp
/* Align the stack and keep aligned for call to bootblock_c_entry() */ @@ -53,7 +54,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */
- post_code(0xa2) + post_code(POST_ENTRY_C_BOOTBLOCK)
call bootblock_c_entry
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..be45463 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -75,6 +75,7 @@ cbmem_initted = !cbmem_recovery(cb->s3resume);
if (cb->s3resume && !cbmem_initted) { + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_EMERG, "Unable to recover CBMEM\n"); halt(); } @@ -84,6 +85,7 @@ postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE); recover_postcar_frame(&pcf, cb->s3resume);
+ post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); /* We do not return. */ } diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580..7691033 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -32,10 +32,11 @@ movd %eax, %mm1
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
/* Cache the rom and update the microcode */ cache_rom: + POST_CAR_CACHE_EVICTION /* Disable cache */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -62,6 +63,7 @@ rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr + post_code(POST_CAR_MTRR_ENABLE)
/* The Google FSP release for Braswell has broken microcode update code and FSP needs the installed microcode revision to be non zero. @@ -132,6 +134,7 @@ cmp $0, %eax jne halt2
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootloader stack */ movl %edx, %esp
@@ -167,7 +170,7 @@ pushl %eax /* tsc[31:0] */
before_romstage: - post_code(0x2A) + post_code(POST_ENTRY_C_BOOTBLOCK)
/* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 9e7865d..1696df0 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -123,7 +123,7 @@ fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ - post_code(0x4F); + post_code(POST_FSP_FAILURE); die("Can't find the FSP!\n"); } } diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dfa3258..8ae4ff7 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -50,7 +50,7 @@ * set to NULL. This indicates that the FSP code will use the UPD * region in the FSP binary. */ - post_code(POST_MEM_PREINIT_PREP_START); + post_code(POST_RAM_INIT); fsp_header = params->chipset_context; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); @@ -110,7 +110,7 @@ post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); mainboard_after_memory_init(); - post_code(0x37); + post_code(POST_MAINBOARD_SOC_INIT_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END);
printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); @@ -146,6 +146,7 @@ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes)) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ /* FIXME: A "system" reset is likely enough: */ diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 46df1c8..b8c8c76 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -25,7 +25,7 @@ bool s3wake; struct region_device rdev;
- post_code(0x32); + post_code(POST_ENTRY_ROMSTAGE);
timestamp_add_now(TS_BEFORE_INITRAM);
@@ -35,7 +35,7 @@
/* Perform remaining SOC initialization */ soc_pre_ram_init(params); - post_code(0x33); + post_code(POST_SOC_RAM_PREINIT);
/* Check recovery and MRC cache */ params->saved_data_size = 0; @@ -100,7 +100,7 @@ .chipset_context = fih, };
- post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE);
timestamp_add_now(TS_START_ROMSTAGE);
@@ -126,13 +126,13 @@ /* Board initialization before and after RAM is enabled */ mainboard_pre_raminit(¶ms);
- post_code(0x31); - + post_code(POST_MEM_PREINIT_EXIT); + post_code(POST_RAM_INIT); /* Initialize memory */ raminit_common(¶ms);
soc_after_ram_init(¶ms); - post_code(0x38); + }
/* Initialize the power state */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 7f5d389..59f84d7 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -72,6 +72,7 @@ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { if (CONFIG(HAVE_ACPI_RESUME)) { + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index c6cd7a4..b357dc0 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -108,7 +108,7 @@ } } if (failures) { - post_code(0xea); + post_code(POST_RAM_TEST_FAIL); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); return 1; } @@ -126,6 +126,7 @@ */ printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); if (ram_bitset_nodie(start)) + post_code(POST_RAM_FAILURE); die("DRAM ERROR"); printk(BIOS_DEBUG, "Done.\n"); } @@ -198,7 +199,7 @@
write_phys(dst, backup); if (fail) { - post_code(0xea); + post_code(POST_RAM_FAILURE); die("RAM INIT FAILURE!\n"); } phys_memory_barrier(); diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index 468c938..7411980 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -10,8 +10,7 @@
void bootblock_mainboard_early_init(void) { - post_code(0x30); - post_code(0x31); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT);
gpio_100_write8(0x1, 0x98);
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc..6883e13 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -10,7 +10,7 @@ { u8 byte;
- post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE);
/* turn on secondary smbus at b20 */ pm_write8(0x28, pm_read8(0x28) | 1); diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 6b116fd..1b4cf23 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -28,10 +28,10 @@ pm_io_write8(0xd2, 0);
if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - post_code(0x31); console_init(); + post_code(POST_CONSOLE_READY); } }
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 8a1cc03..67eae9f 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -4,5 +4,5 @@
void board_BeforeAgesa(struct sysinfo *cb) { - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 22ed952..7cade85 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -37,7 +37,7 @@ i82801gx_early_init(); pineview_early_init();
- post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE);
s3resume = southbridge_detect_s3_resume();
@@ -58,7 +58,7 @@ timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "Memory initialized\n");
- post_code(0x31); + post_code(POST_MEM_PREINIT_EXIT);
mb_pirq_setup();
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 72c284f..134bce4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -391,7 +391,7 @@
void perform_raminit(int s3resume) { - post_code(0x3a); + post_code(POST_RAM_INIT);
timestamp_add_now(TS_BEFORE_INITRAM);
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1ec54b3..41a92c8 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -335,7 +335,7 @@ devicetree_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data);
- post_code(0x3a); + post_code(POST_ROM_PEI_DATA_FILL);
/* Fill after mainboard_fill_pei_data as it might provide spd_data */ pei_data.dimm_channel0_disabled = @@ -364,6 +364,7 @@ pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); + post_code(POST_ROM_SDRAM_INIT);
/* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index b9841b5..0dd7204 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -34,6 +34,7 @@ { int s3resume = 0;
+ post_code(POST_ENTRY_ROMSTAGE); if (MCHBAR16(SSKPD_HI) == 0xCAFE) system_reset();
@@ -55,11 +56,11 @@
elog_boot_notify(s3resume);
- post_code(0x38); + post_code(POST_ROM_SOC_EARLY_INIT);
mainboard_early_init(s3resume);
- post_code(0x39); + post_code(POST_RAM_INIT);
perform_raminit(s3resume);
@@ -74,9 +75,9 @@ southbridge_rcba_config(); mainboard_late_rcba_config();
- post_code(0x3d); + post_code(POST_ROM_RCBA_CONFIG);
northbridge_romstage_finalize(s3resume);
- post_code(0x3f); + post_code(POST_ROM_STAGE_HANDOFF); } diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S index 5c186f1..7d21cfe 100644 --- a/src/soc/amd/picasso/bootblock/pre_c.S +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -10,7 +10,7 @@
.global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_ENTRY_BOOTBLOCK_STACK)
movl $_eearlyram_stack, %esp
@@ -23,7 +23,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */
- post_code(0xa2) + post_code(POST_ENTRY_C_BOOTBLOCK)
call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 83243d3..bfe395a 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -75,10 +75,10 @@ { int s3_resume;
- post_code(0x40); + post_code(POST_ENTRY_ROMSTAGE); console_init();
- post_code(0x41); + post_code(POST_CONSOLE_READY); s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); @@ -87,14 +87,14 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
- post_code(0x43); + post_code(POST_FSP_MEMORY_INIT); fsp_memory_init(s3_resume); soc_update_mrc_cache();
memmap_stash_early_dram_usage();
- post_code(0x44); + post_code(POST_ENTRY_RAMSTAGE); run_ramstage();
- post_code(0x50); /* Should never see this post code. */ + post_code(POST_RAMSTAGE_DIE); /* Should never see this post code. */ } diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 4025f80..ba2fe08 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -85,7 +85,7 @@ */ sb_reset_i2c_slaves(); bootblock_fch_early_init(); - post_code(0x90); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); }
void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 909b847..b49b3af 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -145,11 +145,11 @@ if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
- post_code(0x47); + post_code(POST_AGESA_INIT_ENV); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ - post_code(0x46); + post_code(POST_AGESA_S3_RESTORE); do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103ef..c3baf46 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -33,10 +33,10 @@
static void agesa_call(void) { - post_code(0x37); + post_code(POST_ROM_SOC_INIT_RESET); do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
- post_code(0x38); + post_code(POST_ROM_SOC_EARLY_INIT); /* APs will not exit amdinitearly */ do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } @@ -58,6 +58,7 @@ int i;
console_init(); + post_code(POST_CONSOLE_READY);
soc_enable_psp_early(); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) @@ -111,8 +112,9 @@ post_code(0x42); psp_notify_dram();
- post_code(0x43); + post_code(POST_PSP_DRAM_NOTIFY); if (cbmem_recovery(s3_resume)) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); @@ -120,8 +122,9 @@ if (CONFIG(SMM_TSEG)) smm_list_regions();
- post_code(0x44); + post_code(POST_ENTRY_POST_CAR); if (postcar_frame_init(&pcf, 0)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n");
/* @@ -139,10 +142,10 @@ /* Cache the TSEG region */ postcar_enable_tseg_cache(&pcf);
- post_code(0x45); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf);
- post_code(0x50); /* Should never see this post code. */ + post_code(POST_RAMSTAGE_DIE); /* Should never see this post code. */ }
void SetMemParams(AMD_POST_PARAMS *PostParams) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 2137e49..6e57266 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <spi-generic.h> +#include <console/console.h>
static const struct pad_config tpm_spi_configs[] = { #if CONFIG(SOC_INTEL_GLK) @@ -108,4 +109,5 @@ paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); } + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 1d1bd30..a2c005c 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -167,6 +167,7 @@ cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 8c194fc..c6e2549 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -92,6 +92,7 @@ cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3b7aa40..2d4a033 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -34,7 +34,7 @@ { struct romstage_params rp = { 0 };
- post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE);
/* System Agent Early Initialization */ systemagent_early_init(); @@ -59,7 +59,7 @@ /* Fill in mainboard pei_date. */ mainboard_pre_raminit(&rp);
- post_code(0x32); + post_code(POST_MEM_PREINIT_EXIT);
timestamp_add_now(TS_BEFORE_INITRAM);
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 69ed174..ae2a306 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -12,13 +12,11 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry:
- post_code(0x20) - movl $no_reset, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */
no_reset: - post_code(0x21) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
/* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -31,7 +29,7 @@ wrmsr jnz clear_fixed_mtrr
- post_code(0x22) + post_code(POST_CAR_FIXED_MTRR)
/* Figure put how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -49,7 +47,7 @@ dec %ebx jnz clear_var_mtrr
- post_code(0x23) + post_code(POST_CAR_VARIABLE_MTRR)
/* Configure default memory type to uncacheable (UC) */ mov $MTRR_DEF_TYPE_MSR, %ecx @@ -76,7 +74,7 @@ bts %eax, %esi dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */
- post_code(0x24) + post_code(POST_CAR_MTRR_ENABLE)
#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) /* Configure CAR region as write-back (WB) */ @@ -153,7 +151,7 @@ .global car_init_done car_init_done:
- post_code(0x29) + post_code(POST_ENTRY_BOOTBLOCK_STACK)
/* Setup bootblock stack */ mov $_ecar_stack, %esp @@ -170,7 +168,7 @@ pushl %eax /* tsc[31:0] */
before_carstage: - post_code(0x2A) + post_code(POST_ENTRY_C_BOOTBLOCK)
call bootblock_c_entry /* Never reached */ @@ -203,7 +201,7 @@ or $0x1, %eax wrmsr
- post_code(0x26) + post_code(POST_CAR_CACHE_CLEAR)
/* Clear the cache memory region. This will also fill up the cache */ movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -213,7 +211,7 @@ cld rep stosl
- post_code(0x27) + post_code(POST_CAR_CACHE_EVICTION)
/* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx @@ -221,8 +219,7 @@ or $0x2, %eax wrmsr
- post_code(0x28) - + post_code(POST_CAR_INIT_CACHE) jmp car_init_done
#elif CONFIG(INTEL_CAR_CQOS) @@ -300,7 +297,7 @@ and %ebx, %eax wrmsr
- post_code(0x26) + post_code(POST_CAR_CACHE_CLEAR)
/* Clear the cache memory region. This will also fill up the cache */ movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -325,19 +322,19 @@ and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax wrmsr
- post_code(0x28) + post_code(POST_CAR_INIT_CACHE)
jmp car_init_done
#elif CONFIG(INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced car_nem_enhanced: + post_code(POST_CAR_CACHE_EVICTION) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr - post_code(0x26)
/* Create n-way set associativity of cache */ xorl %edi, %edi @@ -427,7 +424,7 @@ xorl %edx, %edx wrmsr
- post_code(0x27) + post_code(POST_CAR_CACHE_EVICTION) /* * Enable No-Eviction Mode Run State by setting * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. @@ -438,7 +435,6 @@ orl $0x02, %eax wrmsr
- post_code(0x28) - + post_code(POST_CAR_INIT_CACHE) jmp car_init_done #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index b9daf08..1eb0751 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -17,7 +17,7 @@
.global cache_as_ram cache_as_ram: - post_code(0x21) + post_code(POST_BOOTBLOCK_PRE_C_EXIT)
/* find fsp in cbfs */ lea fsp_name, %esi @@ -70,6 +70,7 @@ cmp $0, %eax jnz .halt_forever
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ mov %edx, %esp
@@ -87,6 +88,7 @@ movd %mm1, %eax push %eax
+ post_code(POST_ENTRY_C_BOOTBLOCK) /* We can call into C functions now */ call bootblock_c_entry
diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index fc1c7c9..10484545 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -473,11 +473,12 @@ * edi: High 32-bits of timestamp */
+ post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ movl $_ecar_stack, %esp
before_carstage: - post_code(0x2b) + post_code(POST_ENTRY_C_BOOTBLOCK)
/* Get the timestamp passed in bootblock_crt0.S */ push %edi diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index efe3c10..081eb14 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -17,8 +17,8 @@ { bool s3wake;
- post_code(0x20); console_init(); + post_code(POST_CONSOLE_READY);
if (CONFIG(STORAGE_TEST)) { uint32_t bar; diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 6380db2..bdc2d2e 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -21,6 +21,7 @@
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); }
void bootblock_soc_init(void) diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index 54ad85a..e0ecc03 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -4,6 +4,7 @@ #include <intelblocks/systemagent.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <console/console.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -19,6 +20,7 @@ pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); }
void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index f6653e2..bcb516d 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -48,6 +48,7 @@ uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); }
void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 3db9ca9..c675213 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -25,6 +25,7 @@ unlock_pam_regions();
if (postcar_frame_init(&pcf, 1 * KiB)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n");
/* @@ -40,6 +41,7 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: postcodes: replaced postcode values with their respective defined constants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/p4-netbur... File src/cpu/intel/car/p4-netburst/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/p4-netbur... PS1, Line 216: trailing whitespace
Sindhoor Tilak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: postcodes: replaced postcode values with their respective defined constants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/p4-netbur... File src/cpu/intel/car/p4-netburst/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/p4-netbur... PS1, Line 216:
trailing whitespace
Ack
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: postcodes: replaced postcode values with their respective defined constants ......................................................................
Patch Set 1:
(11 comments)
This commit does way to many things at the same time, making it hard to review.
https://review.coreboot.org/c/coreboot/+/42503/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42503/1//COMMIT_MSG@9 PS1, Line 9: values that should be one commit, as it's only replacing hardcoded numbers with defines it's easy to review. Maybe even the first commit?
https://review.coreboot.org/c/coreboot/+/42503/1/src/arch/x86/postcar.c File src/arch/x86/postcar.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/arch/x86/postcar.c@36 PS1, Line 36: post_code(POST_RAMSTAGE_DIE); is this code reachable? doesn't run_ramstage call die()?
https://review.coreboot.org/c/coreboot/+/42503/1/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/arch/x86/postcar_loader... PS1, Line 101: die please use die_with_post_code()
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/bootblock... File src/cpu/intel/car/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/bootblock... PS1, Line 26: POST_BOOTBLOCK_SOC_EARLYINIT does postcodes need to be send before entering a function, or after all work has been done? That should be defined first and written down somewhere.
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/core2/cac... File src/cpu/intel/car/core2/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/core2/cac... PS1, Line 82: 0x23 that one got lost
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/haswell/romst... File src/cpu/intel/haswell/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/haswell/romst... PS1, Line 22: post_code move before enable_lapic
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/haswell/romst... PS1, Line 48: post_code this one is missing
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/qemu-x86/bootblock.... File src/cpu/qemu-x86/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/qemu-x86/bootblock.... PS1, Line 9: POST_ENTRY_C_BOOTBLOCK that doesn't match the description
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/qemu-x86/bootblock.... PS1, Line 14: post_code move into console_init()
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/broadwell/rom... File src/soc/intel/broadwell/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/broadwell/rom... PS1, Line 37: post_code(POST_ENTRY_ROMSTAGE); move to src/cpu/intel/car/romstage.c
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/skylake/bootb... PS1, Line 24: POST_BOOTBLOCK_SOC_EARLYINIT move to src/lib/bootblock.c
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: postcodes: replaced postcode values with their respective defined constants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42503/1/src/mainboard/bap/ode_e21XX... File src/mainboard/bap/ode_e21XX/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/mainboard/bap/ode_e21XX... PS1, Line 31: post_code(POST_ENTRY_ROMSTAGE); this board is not hooked up for build
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: postcodes: replaced postcode values with their respective defined constants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42503/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42503/1//COMMIT_MSG@7 PS1, Line 7: replaced Present tense imperative mood: Replace.
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#2).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/postcar_loader.c M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/haswell/romstage.c M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/xeon_sp/romstage.c 22 files changed, 79 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/2
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#3).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/postcar_loader.c M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/haswell/romstage.c M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/xeon_sp/romstage.c 22 files changed, 79 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/3
Sindhoor Tilak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 3:
(6 comments)
https://review.coreboot.org/c/coreboot/+/42503/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42503/1//COMMIT_MSG@7 PS1, Line 7: replaced
Present tense imperative mood: Replace.
Ack
https://review.coreboot.org/c/coreboot/+/42503/1//COMMIT_MSG@9 PS1, Line 9: values
that should be one commit, as it's only replacing hardcoded numbers with defines it's easy to review […]
Ack
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/bootblock... File src/cpu/intel/car/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/cpu/intel/car/bootblock... PS1, Line 26: POST_BOOTBLOCK_SOC_EARLYINIT
does postcodes need to be send before entering a function, or after all work has been done? That sho […]
Ack
https://review.coreboot.org/c/coreboot/+/42503/1/src/mainboard/bap/ode_e21XX... File src/mainboard/bap/ode_e21XX/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/mainboard/bap/ode_e21XX... PS1, Line 31: post_code(POST_ENTRY_ROMSTAGE);
this board is not hooked up for build
Ack
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/broadwell/rom... File src/soc/intel/broadwell/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/broadwell/rom... PS1, Line 37: post_code(POST_ENTRY_ROMSTAGE);
move to src/cpu/intel/car/romstage. […]
Ack
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42503/1/src/soc/intel/skylake/bootb... PS1, Line 24: POST_BOOTBLOCK_SOC_EARLYINIT
move to src/lib/bootblock. […]
Ack
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#4).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/postcar_loader.c M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/haswell/romstage.c M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/xeon_sp/romstage.c 22 files changed, 79 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/4
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 4: Code-Review+1
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Paul Menzel, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#5).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/postcar_loader.c M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/xeon_sp/romstage.c 28 files changed, 92 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/5
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Paul Menzel, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#6).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/google/auron/ec.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/link/ec.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/ec.c M src/mainboard/intel/strago/ec.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/southbridge/intel/common/finalize.c 38 files changed, 105 insertions(+), 109 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/6
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42503/6/src/cpu/intel/car/non-evict... File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/6/src/cpu/intel/car/non-evict... PS6, Line 16: post_code(POST_BOOTBLOCK_PRE_C_ENTRY) Moved. I think this is fine.
https://review.coreboot.org/c/coreboot/+/42503/6/src/cpu/intel/car/non-evict... PS6, Line 181: post_code(POST_CAR_CACHE_EVICTION) Moved. This appears to be fine, but you need to keep in mind this changes the value of %eax register.
Here, it is followed by rdmsr which reloads %eax.
Sindhoor Tilak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42503/6/src/cpu/intel/car/non-evict... File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/6/src/cpu/intel/car/non-evict... PS6, Line 16: post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
Moved. I think this is fine.
Ack
https://review.coreboot.org/c/coreboot/+/42503/6/src/cpu/intel/car/non-evict... PS6, Line 181: post_code(POST_CAR_CACHE_EVICTION)
Moved. […]
Ack
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Paul Menzel, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#7).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/google/auron/ec.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/link/ec.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/ec.c M src/mainboard/intel/strago/ec.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/southbridge/intel/common/finalize.c 39 files changed, 106 insertions(+), 110 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/7
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Paul Menzel, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#9).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/google/auron/ec.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/link/ec.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/ec.c M src/mainboard/intel/strago/ec.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/southbridge/intel/common/finalize.c 39 files changed, 107 insertions(+), 110 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/9
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... File src/cpu/intel/car/non-evict/exit_car.S:
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... PS9, Line 15: POST_CAR_CACHE_DISABLE That post code had been already used in bootblock
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... PS9, Line 28: POST_CAR_CACHE_EVICTION That postcode had been already used in bootblock and had a different meaning. Note here it's turned off, while it was turned on in bootblock. Please add a new postcode for postcard stage/car teardown
Sindhoor Tilak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... File src/cpu/intel/car/non-evict/exit_car.S:
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... PS9, Line 15: POST_CAR_CACHE_DISABLE
That post code had been already used in bootblock
Ack
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... PS9, Line 28: POST_CAR_CACHE_EVICTION
That postcode had been already used in bootblock and had a different meaning. […]
Ack
Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Paul Menzel, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#10).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/google/auron/ec.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/link/ec.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/ec.c M src/mainboard/intel/strago/ec.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/southbridge/intel/common/finalize.c 39 files changed, 105 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/10
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 10:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/core2/ca... File src/cpu/intel/car/core2/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/core2/ca... PS10, Line 50: post_code(POST_CAR_VARIABLE_MTRR) Must not load %eax here. Also no point doing this multiple times inside a loop.
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p3/cache... File src/cpu/intel/car/p3/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p3/cache... PS10, Line 37: post_code(POST_CAR_VARIABLE_MTRR) Must not load %eax here and place outside the loop.
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p4-netbu... File src/cpu/intel/car/p4-netburst/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p4-netbu... PS10, Line 46: post_code(POST_CAR_VARIABLE_MTRR) Like before
https://review.coreboot.org/c/coreboot/+/42503/10/src/southbridge/intel/comm... File src/southbridge/intel/common/finalize.c:
https://review.coreboot.org/c/coreboot/+/42503/10/src/southbridge/intel/comm... PS10, Line 3: #include <arch/io.h> I think this was for outb() and no longer needed.
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 10: Code-Review+1
Hello build bot (Jenkins), Damien Zammit, Frans Hendriks, Lee Leahy, Paul Menzel, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42503
to look at the new patch set (#11).
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
post_code: replace postcode values with their respective defined constants
* Replace existing post_code call values with their defined constants * Reorganize certain post_code calls to match their respective defines * Updated define values reflect the newer changes to post_codes.h
Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/tables.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/google/auron/ec.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/link/ec.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/ec.c M src/mainboard/intel/strago/ec.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/southbridge/intel/common/finalize.c 39 files changed, 105 insertions(+), 109 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/11
Sindhoor Tilak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 11:
(6 comments)
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/core2/ca... File src/cpu/intel/car/core2/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/core2/ca... PS10, Line 50: post_code(POST_CAR_VARIABLE_MTRR)
Must not load %eax here. Also no point doing this multiple times inside a loop.
Done
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... File src/cpu/intel/car/non-evict/exit_car.S:
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... PS9, Line 15: POST_CAR_CACHE_DISABLE
Ack
Done
https://review.coreboot.org/c/coreboot/+/42503/9/src/cpu/intel/car/non-evict... PS9, Line 28: POST_CAR_CACHE_EVICTION
Ack
Done
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p3/cache... File src/cpu/intel/car/p3/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p3/cache... PS10, Line 37: post_code(POST_CAR_VARIABLE_MTRR)
Must not load %eax here and place outside the loop.
Done
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p4-netbu... File src/cpu/intel/car/p4-netburst/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/10/src/cpu/intel/car/p4-netbu... PS10, Line 46: post_code(POST_CAR_VARIABLE_MTRR)
Like before
Done
https://review.coreboot.org/c/coreboot/+/42503/10/src/southbridge/intel/comm... File src/southbridge/intel/common/finalize.c:
https://review.coreboot.org/c/coreboot/+/42503/10/src/southbridge/intel/comm... PS10, Line 3: #include <arch/io.h>
I think this was for outb() and no longer needed.
Did you mean post_codes.h? I added console.h for the post_code() call
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42503/10/src/southbridge/intel/comm... File src/southbridge/intel/common/finalize.c:
https://review.coreboot.org/c/coreboot/+/42503/10/src/southbridge/intel/comm... PS10, Line 3: #include <arch/io.h>
Did you mean post_codes.h? I added console. […]
No, I meant <arch/io.h>, you removed outb() call here. But someone could/should make a decision that <console/console.h> is acceptable indirect include for <console/postcodes.h> indeed.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 11:
(64 comments)
I've marked all comments about "Why is this moved?" and "Missed this one?" as resolved because there's lots of them. This commit is very large and so thus very hard to review. I would not dare submit it as I am not sure if it could break something, like what Kyösti said about clobbering eax.
https://review.coreboot.org/c/coreboot/+/42503/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42503/11//COMMIT_MSG@7 PS11, Line 7: post_code: replace postcode values with their respective defined constants Reading this commit summary, I'd expect that this commit only does one thing: replace `post_code(0xFOO)` with `post_code(POST_FOO)`. However, it does more than that, and since it touches everything at once, it's hard to review.
Plus, if there's a list of things in a commit message, it's a good sign that they should be split up in separate commits.
https://review.coreboot.org/c/coreboot/+/42503/11//COMMIT_MSG@9 PS11, Line 9: Replace existing post_code call values with their defined constants If this is only about replacing hex numbers with equivalent macros (same value), it should be reproducible (result in the exact same coreboot binaries built with `BUILD_TIMELESS=1` or `abuild --timeless`). It would be good if this change could be in its own commit so that it can be verified easily.
https://review.coreboot.org/c/coreboot/+/42503/11//COMMIT_MSG@10 PS11, Line 10: Reorganize certain post_code calls to match their respective defines I would prefer to handle this on a platform-by-platform basis, especially because changing assembly code could accidentally result in clobbered registers. Plus, I've got questions as to why certain postcode prints were moved and why some others were left unchanged (still using hex values). The reasoning behind all those decisions would be easier to explain in the multiple commit messages of smaller commits.
https://review.coreboot.org/c/coreboot/+/42503/11//COMMIT_MSG@11 PS11, Line 11: Updated define values reflect the newer changes to post_codes.h I don't see anything like that anywhere.
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/core2/ca... File src/cpu/intel/car/core2/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/core2/ca... PS11, Line 90: post_code(0x24) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/non-evic... File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/non-evic... PS11, Line 16: post_code(POST_BOOTBLOCK_PRE_C_ENTRY) Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/non-evic... PS11, Line 95: post_code(0x24) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/non-evic... PS11, Line 181: post_code(POST_CAR_CACHE_EVICTION) Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/non-evic... File src/cpu/intel/car/non-evict/exit_car.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/non-evic... PS11, Line 28: post_code(POST_EXIT_CAR_EVICTION_DISABLE) Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/non-evic... PS11, Line 37: post_code(0x32) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p3/cache... File src/cpu/intel/car/p3/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p3/cache... PS11, Line 51: post_code(0x22) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... File src/cpu/intel/car/p4-netburst/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 60: post_code(0x22) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 118: post_code(0x24) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 153: post_code(0x25) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 168: post_code(0x26) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 184: post_code(0x27) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 191: post_code(0x28) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 199: post_code(0x29) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 342: post_code(POST_CAR_CACHE_CLEAR) Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... File src/cpu/intel/car/p4-netburst/exit_car.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 20: post_code(0x31) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/intel/car/p4-netbu... PS11, Line 28: post_code(0x32) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/qemu-x86/cache_as_... File src/cpu/qemu-x86/cache_as_ram_bootblock.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/qemu-x86/cache_as_... PS11, Line 15: post_code(POST_CAR_CACHE_CLEAR) Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/x86/mtrr/mtrr.c File src/cpu/x86/mtrr/mtrr.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/cpu/x86/mtrr/mtrr.c@81... PS11, Line 813: post_code(POST_BOOTBLOCK_MTRR_CHECK); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/device/pci_device.c File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/device/pci_device.c@13... PS11, Line 1313: post_code(POST_PCI_SCAN_BRIDGES_ENTRY); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/drivers/intel/fsp1_1/c... File src/drivers/intel/fsp1_1/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/drivers/intel/fsp1_1/c... PS11, Line 19: post_code(POST_BOOTBLOCK_PRE_C_ENTRY) Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/drivers/intel/fsp1_1/r... File src/drivers/intel/fsp1_1/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/drivers/intel/fsp1_1/r... PS11, Line 37: post_code(POST_SOC_RAM_PREINIT_ENTRY); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/drivers/intel/fsp1_1/r... PS11, Line 103: post_code(0x30); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/drivers/intel/fsp1_1/r... PS11, Line 126: post_code(POST_BOARD_PREINIT_ENTRY); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/drivers/intel/fsp1_1/r... PS11, Line 133: post_code(POST_MAINBOARD_SOC_INIT_ENTRY); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/amd/thatcher... File src/mainboard/amd/thatcher/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/amd/thatcher... PS11, Line 13: post_code(0x30); It would make more sense to drop this unnecessary post_code call before this commit. I think it is dropped from several other places in CB:43132, because it is emitted elsewhere in common code?
It would be good (easier to review) to have a commit that drops unneeded `post_code(0x30)` calls and explains *why* in the commit message.
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/auron... File src/mainboard/google/auron/ec.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/auron... PS11, Line 31: post_code(0xf1); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/cyan/... File src/mainboard/google/cyan/ec.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/cyan/... PS11, Line 24: post_code(0xf1); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/link/... File src/mainboard/google/link/ec.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/link/... PS11, Line 23: post_code(0xf1); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/rambi... File src/mainboard/google/rambi/ec.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/rambi... PS11, Line 25: post_code(0xf1); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/slipp... File src/mainboard/google/slippy/ec.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/google/slipp... PS11, Line 30: post_code(0xf1); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/intel/strago... File src/mainboard/intel/strago/ec.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/mainboard/intel/strago... PS11, Line 24: post_code(0xf1); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/hasw... File src/northbridge/intel/haswell/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/hasw... PS11, Line 43: post_code(0x3a); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/hasw... PS11, Line 55: post_code(POST_ROM_SDRAM_INIT); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/hasw... PS11, Line 79: post_code(0x3f); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/pine... File src/northbridge/intel/pineview/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/pine... PS11, Line 56: post_code(POST_ROM_SDRAM_INIT); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/pine... PS11, Line 64: post_code(POST_ROM_RCBA_CONFIG); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/sand... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/sand... PS11, Line 333: post_code(POST_ROM_PEI_DATA_FILL); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/sand... File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/sand... PS11, Line 77: post_code(0x3d); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/northbridge/intel/sand... PS11, Line 81: post_code(0x3f); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/picasso/bootbl... File src/soc/amd/picasso/bootblock/pre_c.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/picasso/bootbl... PS11, Line 7: post_code(0xb0) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/picasso/romsta... File src/soc/amd/picasso/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/picasso/romsta... PS11, Line 82: post_code(0x41); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/picasso/romsta... PS11, Line 86: post_code(0x Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/bo... File src/soc/amd/stoneyridge/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/bo... PS11, Line 86: post_code(POST_BOOTBLOCK_SOC_EARLYINIT); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ch... File src/soc/amd/stoneyridge/chip.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ch... PS11, Line 144: post_code(0x46); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ro... File src/soc/amd/stoneyridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ro... PS11, Line 72: post_code(0x40); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ro... PS11, Line 75: post_code(0x41); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ro... PS11, Line 105: post_code(0x60); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ro... PS11, Line 108: post_code(0x61); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ro... PS11, Line 114: post_code(0x43); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/amd/stoneyridge/ro... PS11, Line 123: post_code(0x44); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/broadwell/ro... File src/soc/intel/broadwell/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/broadwell/ro... PS11, Line 37: post_code(0x30); Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/broadwell/ro... PS11, Line 59: post_code(POST_MEM_PREINIT_PREP_START); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/common/block... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/common/block... PS11, Line 52: post_code(0x23) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/common/block... PS11, Line 79: post_code(0x24) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/common/block... PS11, Line 156: post_code(0x29) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/common/block... PS11, Line 340: post_code(0x26) Missed this one?
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/quark/romsta... File src/soc/intel/quark/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/soc/intel/quark/romsta... PS11, Line 37: post_code(POST_FSP_MEMORY_INIT); Why is this moved?
https://review.coreboot.org/c/coreboot/+/42503/11/src/southbridge/intel/comm... File src/southbridge/intel/common/finalize.c:
https://review.coreboot.org/c/coreboot/+/42503/11/src/southbridge/intel/comm... PS11, Line 4: #include <console/console.h> I don't think you meant to change this include?
https://review.coreboot.org/c/coreboot/+/42503/11/src/southbridge/intel/comm... PS11, Line 51: post_code(POST_OS_BOOT); I'd replace this outb() in its own commit for reproducibility
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42503 )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42503/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42503/11//COMMIT_MSG@9 PS11, Line 9: Replace existing post_code call values with their defined constants
If this is only about replacing hex numbers with equivalent macros (same value), it should be reprod […]
Forget about reproducibility... I see that most postcode values are changed...
In that case, it would make more sense to define and use postcodes in the same commit, a few postcodes (e.g. postcodes for a single stage) at a time.
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42503?usp=email )
Change subject: post_code: replace postcode values with their respective defined constants ......................................................................
Abandoned
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Frans Hendriks (Code Review)
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HAOUAS Elyes (Code Review)
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Kyösti Mälkki (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)
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Sindhoor Tilak (Code Review)
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Stefan Reinauer (Code Review)