Change in coreboot[master]: mb/intel/tglrvp: pin mux for ISH

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38622 )

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

mb/intel/tglrvp: pin mux for ISH

pin mux for ISHUART0, ISHI2C0, ISHGPIO0-7

BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux

Signed-off-by: Wonkyu Kim 
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38622/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index 69bb931..5806b3c 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -28,6 +28,24 @@
    PAD_CFG_GPO(GPP_C15, 0, PLTRST),
    PAD_CFG_GPO(GPP_R6, 0, PLTRST),
    PAD_CFG_GPO(GPP_H12, 0, PLTRST),
+
+	/* ISH UART0 RX/TX */
+	PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+
+	/* ISH I2C0 */
+	PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+
+	/* ISH GPI 0-6 */
+	PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
 };

/* Early pad configuration in bootblock */

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38622 )

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

Patch Set 1: Code-Review+1

[Wonkyu Kim (Code Review)]

Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Nick Vaccaro, Shaunak Saha, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38622

to look at the new patch set (#2).

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

mb/intel/tglrvp: pin mux for ISH

pin mux for ISHUART0, ISHI2C0, ISHGPIO0-7
TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux.

BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux

Signed-off-by: Wonkyu Kim 
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38622/2

[Wonkyu Kim (Code Review)]

Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Nick Vaccaro, build bot (Jenkins), Shaunak Saha, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38622

to look at the new patch set (#3).

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

mb/intel/tglrvp: pin mux for ISH

pin mux for ISHUART0, ISHI2C0, ISHGPIO0-7
TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux.

BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux

Signed-off-by: Wonkyu Kim 
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38622/3

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38622 )

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

Patch Set 3: Code-Review+1

Rebased to fix merge conflict

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38622 )

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38622/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38622/3//COMMIT_MSG@7 
PS3, Line 7: mb/intel/tglrvp: pin mux for ISH
Please make this a statement.

https://review.coreboot.org/c/coreboot/+/38622/3//COMMIT_MSG@16 
PS3, Line 16: TEST=Build and boot to OS and check pinctl driver to check pin mux
Please elaborate how.

[Wonkyu Kim (Code Review)]

Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Nick Vaccaro, build bot (Jenkins), Shaunak Saha, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38622

to look at the new patch set (#4).

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

mb/intel/tglrvp: pin mux for ISH

TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c.

Pin mux for ISH for TGLRVP
ISHUART0: GPP_D13, GPP_D14 as NF1
ISHI2C0: GPP_B5, GPP_B6 as NF1
ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1

BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux.
Check ISHUART0, ISHI2C0, ISHGPIO0-7 Native function setting.
They should be NF1.

Signed-off-by: Wonkyu Kim 
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38622/4

[Wonkyu Kim (Code Review)]

Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Nick Vaccaro, build bot (Jenkins), Shaunak Saha, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38622

to look at the new patch set (#5).

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

mb/intel/tglrvp: pin mux for ISH

TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c.

Pin mux for ISH for TGLRVP
ISHUART0: GPP_D13, GPP_D14 as NF1
ISHI2C0: GPP_B5, GPP_B6 as NF1
ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1

BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux.
Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting.
They should be NF1.

Signed-off-by: Wonkyu Kim 
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38622/5

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38622 )

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38622/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38622/3//COMMIT_MSG@7 
PS3, Line 7: mb/intel/tglrvp: pin mux for ISH
> Please make this a statement.

Done

https://review.coreboot.org/c/coreboot/+/38622/3//COMMIT_MSG@16 
PS3, Line 16: TEST=Build and boot to OS and check pinctl driver to check pin mux
> Please elaborate how.

Done

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38622 )

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

Patch Set 5: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38622 )

Change subject: mb/intel/tglrvp: pin mux for ISH
......................................................................

mb/intel/tglrvp: pin mux for ISH

TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c.

Pin mux for ISH for TGLRVP
ISHUART0: GPP_D13, GPP_D14 as NF1
ISHI2C0: GPP_B5, GPP_B6 as NF1
ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1

BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux.
Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting.
They should be NF1.

Signed-off-by: Wonkyu Kim 
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622
Tested-by: build bot (Jenkins) 
Reviewed-by: Nick Vaccaro 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index d1dc4ca..8638b80 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -32,6 +32,24 @@
    /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
    PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
    PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
+
+	/* ISH UART0 RX/TX */
+	PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+
+	/* ISH I2C0 */
+	PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+
+	/* ISH GPI 0-6 */
+	PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
 };

/* Early pad configuration in bootblock */