Wonkyu Kim has uploaded this change for review.

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mb/intel/tglrvp: pin mux for ISH

pin mux for ISHUART0, ISHI2C0, ISHGPIO0-7

BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38622/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index 69bb931..5806b3c 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -28,6 +28,24 @@
 	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
 	PAD_CFG_GPO(GPP_R6, 0, PLTRST),
 	PAD_CFG_GPO(GPP_H12, 0, PLTRST),
+
+	/* ISH UART0 RX/TX */
+	PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+
+	/* ISH I2C0 */
+	PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+
+	/* ISH GPI 0-6 */
+	PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
 };
 
 /* Early pad configuration in bootblock */

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