Patrick Georgi submitted this change.
mb/intel/tglrvp: pin mux for ISH
TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c.
Pin mux for ISH for TGLRVP
ISHUART0: GPP_D13, GPP_D14 as NF1
ISHI2C0: GPP_B5, GPP_B6 as NF1
ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1
BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux.
Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting.
They should be NF1.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
1 file changed, 18 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index d1dc4ca..8638b80 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -32,6 +32,24 @@
/* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
+
+ /* ISH UART0 RX/TX */
+ PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+
+ /* ISH I2C0 */
+ PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+
+ /* ISH GPI 0-6 */
+ PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
};
/* Early pad configuration in bootblock */
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