Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
soc/amd: move non-CAR linker scripts to common directory
AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar.
TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries.
Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/cpu/Kconfig R src/soc/amd/common/block/cpu/noncar/memlayout.ld R src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld R src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc R src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig 6 files changed, 19 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/47828/1
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index f6756e1..826f80b 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -11,3 +11,19 @@ This is only used for AMD CPU before family 17h. From family 17h on the RAM is already initialized by the PSP before the x86 cores are released from reset. + +config SOC_AMD_COMMON_BLOCK_NONCAR + bool + default n + help + From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any + more, since the RAM initialization is already done by the PSP when + the x86 cores are released from reset. + +if SOC_AMD_COMMON_BLOCK_NONCAR + +config MEMLAYOUT_LD_FILE + string + default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" + +endif # SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/common/block/cpu/noncar/memlayout.ld similarity index 100% rename from src/soc/amd/picasso/memlayout.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout.ld diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld similarity index 93% rename from src/soc/amd/picasso/memlayout_psp_verstage.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld index ca95cf8..aa27bae 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld @@ -4,6 +4,8 @@ #include <soc/psp_transfer.h> #include <fmap_config.h>
+/* TODO: Move defines to SoC-specific header file to allow SoC specific values if needed. */ + /* * Start of available space is 0x15000 and this is where the * header for the user app (verstage) must be mapped. diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc similarity index 100% rename from src/soc/amd/picasso/memlayout_transfer_buffer.inc rename to src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld similarity index 100% rename from src/soc/amd/picasso/memlayout_x86.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d7d2a6..6fa3664 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO @@ -57,10 +58,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS
-config MEMLAYOUT_LD_FILE - string - default "src/soc/amd/picasso/memlayout.ld" - config EARLY_RESERVED_DRAM_BASE hex default 0x2000000
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 1:
i'm planning to move the picasso boot block to soc/amd/common/block/cpu/noncar as well, but before doing that i'd like to know if you like the direction this moves or if you have any better ideas for this
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
soc/amd: move non-CAR linker scripts to common directory
AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar.
TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries.
Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/common/block/cpu/Kconfig R src/soc/amd/common/block/cpu/noncar/memlayout.ld R src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld R src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc R src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig 6 files changed, 19 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index f6756e1..826f80b 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -11,3 +11,19 @@ This is only used for AMD CPU before family 17h. From family 17h on the RAM is already initialized by the PSP before the x86 cores are released from reset. + +config SOC_AMD_COMMON_BLOCK_NONCAR + bool + default n + help + From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any + more, since the RAM initialization is already done by the PSP when + the x86 cores are released from reset. + +if SOC_AMD_COMMON_BLOCK_NONCAR + +config MEMLAYOUT_LD_FILE + string + default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" + +endif # SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/common/block/cpu/noncar/memlayout.ld similarity index 100% rename from src/soc/amd/picasso/memlayout.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout.ld diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld similarity index 93% rename from src/soc/amd/picasso/memlayout_psp_verstage.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld index ca95cf8..aa27bae 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld @@ -4,6 +4,8 @@ #include <soc/psp_transfer.h> #include <fmap_config.h>
+/* TODO: Move defines to SoC-specific header file to allow SoC specific values if needed. */ + /* * Start of available space is 0x15000 and this is where the * header for the user app (verstage) must be mapped. diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc similarity index 100% rename from src/soc/amd/picasso/memlayout_transfer_buffer.inc rename to src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld similarity index 100% rename from src/soc/amd/picasso/memlayout_x86.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d7d2a6..6fa3664 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO @@ -57,10 +58,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS
-config MEMLAYOUT_LD_FILE - string - default "src/soc/amd/picasso/memlayout.ld" - config EARLY_RESERVED_DRAM_BASE hex default 0x2000000
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 32: * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10 Is this correct?
There is assert on:
BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 == X86_RESET_VECTOR
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 85: _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); The assertion here reveals redundancy in the use of Kconfigs. You do not need to define X86_RESET_VECTOR separately. Also X86_RESET_VECTOR help text forgets to mention there is architectural requirement for the address to end with 0xfff0.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); Is this correct?
The architectural requirement is for X86_RESET_VECTOR to have the traditional IP 0xfff0. So it is the end of bootblock that must be at 64KiB boundary. AFAICS, C_ENV_BOOTBLOCK_SIZE has no requirements on alignment, so 16 bytes might a sufficient and convenient alignment for BOOTBLOCK_ADDR.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 32: * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
Is this correct? […]
the reset vector isn't in romstage, but in bootblock, so this is wrong. not sure if that comment is still from the hybrid romstage idea that got discarded in the end to fit better into the coreboot model. will look into that and fix it
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 85: _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
The assertion here reveals redundancy in the use of Kconfigs. […]
i agree that that's something i should look into
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
Is this correct? […]
not 100% certain on this and couldn't find a definite answer at the places i thought it was most likely to find some info on that. might be worth to verify if there's a requirement on the base address/granularity, but right now it's not a priority for me, since using stricter alignment/granularity requirements than necessary won't really hurt
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47828/2//COMMIT_MSG@13 PS2, Line 13: will be Twice in the sentence.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 32: * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
the reset vector isn't in romstage, but in bootblock, so this is wrong. […]
Yes, this comment needs update. It was from back when romstage was the first stage to start on x86 (changes were only in chromium tree, but while porting to upstream, the comment wasn't fixed).
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
not 100% certain on this and couldn't find a definite answer at the places i thought it was most lik […]
Seems to be coming from: https://review.coreboot.org/c/coreboot/+/42885
+Raul.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
Seems to be coming from: https://review.coreboot.org/c/coreboot/+/42885 […]
Looking back at this, it does seem overly constrained. I think I was trying in a round about way to enforce CONFIG_C_ENV_BOOTBLOCK_SIZE < 64KiB and that the reset vector landed on a 64 KiB boundary. I would be fine cleaning it up in a follow up.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 32: * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
Yes, this comment needs update. […]
addressed in CB:48307
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
Looking back at this, it does seem overly constrained. […]
Is it a flaw that .reset and the entire uncompressed bootblock appears at end of coreboot.rom for google/zork variants? The Taken execution path is the compressed bootblock embedded in amdfw.rom?
For the traditional x86 bootflow I am attempting to get rid of C_ENV_BOOTBLOCK_SIZE to pack coreboot.rom more efficiently and avoid cases where the static size has to be increased when e.g. bootblock console or other debugging is enabled.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
Is it a flaw that .reset and the entire uncompressed bootblock appears at end of coreboot. […]
Your analysis is correct. We don't need to have bootblock at the end of coreboot.rom. I think Aaron was going to remove it, but I don't think that he did.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
Your analysis is correct. We don't need to have bootblock at the end of coreboot.rom. […]
or does that have something to do with the ID(?) section? it would be sufficient to just have that section at the end of the flash, but i don't know how easy or difficult it is to just generate that section and put it at the end of the image and how well that'll work with the vboot a/b/ro sections
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
or does that have something to do with the ID(?) section? it would be sufficient to just have that s […]
That .id section was already dropped in this memlayout_x86.ld file, it was assumed bootblock would not appear at end of coreboot.rom with soc/picasso. But util/cbfstool still modifies last 12 bytes so it has to remain reserved from free CBFS space.
I see no point implementing .id section support here. One has to use a very fresh flashrom build with amd/picasso, at least Julius was in favor of using a regular textfile in CBFS with the required strings. CB:47602
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 86: _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
The architectural requirement is for X86_RESET_VECTOR to have the traditional IP 0xfff0. So it is the end of bootblock that must be at 64KiB boundary.
I agree, I believe it's only the reset vector we should assert. According to the PSP BIOS design guide * Reset vector is BIOS image base + size - 0x10 * x86's F000 segment's base address is reset vector + 0x10 - 64K, size of 64K * x86's CS reset state is 0xfff0
I don't see a need to assert any requirements on the base address of bootblock. (It was surely added out of caution and has remained.) I tried Mandolin with BOOTBLOCK_ADDR 0x4000 higher and C_ENV_BB_SIZE=0xc000. The system booted OK.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47828 )
Change subject: soc/amd: move non-CAR linker scripts to common directory ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/47828/2/src/soc/amd/common/block/cp... PS2, Line 85: _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
i agree that that's something i should look into
CB:48405 and CB:48406
-
Felix Held (Code Review) -
Furquan Shaikh (Code Review)
-
Kyösti Mälkki (Code Review)
-
Marshall Dawson (Code Review)
-
Paul Menzel (Code Review)
-
Raul Rangel (Code Review)