Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci driver.
BUG=b:154756391 TEST=Made sure trembyle compiles
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/include/soc/mainboard.h A src/soc/amd/picasso/mainboard.c A src/soc/amd/picasso/xhci.c 5 files changed, 85 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43332/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d07af6..1e7f3ef 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -18,6 +18,7 @@ select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES select DRIVERS_I2C_DESIGNWARE + select DRIVERS_USB_PCI_XHCI select GENERIC_GPIO_LIB select IDT_IN_EVERY_STAGE select IOAPIC diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 060f78d..45ded6d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -77,6 +77,8 @@ ramstage-y += config.c ramstage-y += update_microcode.c ramstage-y += graphics.c +ramstage-y += mainboard.c +ramstage-y += xhci.c
smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/soc/amd/picasso/include/soc/mainboard.h b/src/soc/amd/picasso/include/soc/mainboard.h new file mode 100644 index 0000000..55154d8 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/mainboard.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PICASSO_MAINBOARD_H__ +#define __PICASSO_MAINBOARD_H__ + +#include <stddef.h> +#include <soc/smi.h> + +/* + * Returns the GPE table for non GPIO devices. + * i.e., GEVENTS above 23 + */ +const struct sci_source *mainboard_get_gpe_table(size_t *num); + +#endif /* __PICASSO_MAINBOARD_H__ */ diff --git a/src/soc/amd/picasso/mainboard.c b/src/soc/amd/picasso/mainboard.c new file mode 100644 index 0000000..717a579 --- /dev/null +++ b/src/soc/amd/picasso/mainboard.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/mainboard.h> + +__weak const struct sci_source *mainboard_get_gpe_table(size_t *num) +{ + return NULL; +} diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c new file mode 100644 index 0000000..9f3ea9b --- /dev/null +++ b/src/soc/amd/picasso/xhci.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/usb/pci_xhci/pci_xhci.h> +#include <soc/mainboard.h> +#include <soc/pci_devs.h> + +static const struct sci_source *get_matching_sci_source(unsigned int sci_type) +{ + const struct sci_source *sci_sources, *sci_source; + size_t sci_count; + unsigned int i; + + sci_sources = mainboard_get_gpe_table(&sci_count); + + if (!sci_sources) + return NULL; + + for (i = 0; i < sci_count; ++i) { + sci_source = &sci_sources[i]; + if (sci_source->scimap == sci_type) + return sci_source; + } + + return NULL; +} + +enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) +{ + const struct sci_source *sci_source; + unsigned int sci_type; + + if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN) + return CB_ERR_ARG; + + if (dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->path.pci.devfn == XHCI0_DEVFN) + sci_type = SMITYPE_XHC0_PME; + else if (dev->path.pci.devfn == XHCI1_DEVFN) + sci_type = SMITYPE_XHC1_PME; + else + return CB_ERR_ARG; + + sci_source = get_matching_sci_source(sci_type); + + if (!sci_source) { + *gpe = -1; + return CB_SUCCESS; + } + + *gpe = sci_source->gpe; + return CB_SUCCESS; +}
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c File src/soc/amd/picasso/xhci.c:
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c@... PS1, Line 15: mainboard_get_gpe_table Should this table be added to device tree? It can be used for both configuring non-GPIO SCIs as well as reporting back to any callers.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c File src/soc/amd/picasso/xhci.c:
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c@... PS1, Line 15: mainboard_get_gpe_table How about we just hard code it here in the soc code and don't let the mainboard customize it?
I did find this comment here: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
Gevent[23:0] are assumed to be mainboard-specific
From a mainboard implementer perspective I would hope that xHCI wakes just works without having to do anything.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c File src/soc/amd/picasso/xhci.c:
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c@... PS1, Line 15: mainboard_get_gpe_table
How about we just hard code it here in the soc code and don't let the mainboard customize it? […]
In my opinion, it is totally fine to keep(hard code) this within the soc/ rather than having mainboard provide it. The SoC should be able to make a decision about all the different controllers i.e. what GEVENT# to assign. Since it also controls exporting this via ACPI, I think it would work just fine.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43332
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci driver.
BUG=b:154756391 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/xhci.c 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43332/2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c File src/soc/amd/picasso/xhci.c:
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c@... PS1, Line 15: mainboard_get_gpe_table
In my opinion, it is totally fine to keep(hard code) this within the soc/ rather than having mainboa […]
Done
This feels a lot cleaner and encapsulated.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43332/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43332/2//COMMIT_MSG@12 PS2, Line 12: BUG=b:154756391 Can you please add b:160651028 as well?
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c File src/soc/amd/picasso/xhci.c:
https://review.coreboot.org/c/coreboot/+/43332/1/src/soc/amd/picasso/xhci.c@... PS1, Line 15: mainboard_get_gpe_table
Done […]
Agreed!
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43332
to look at the new patch set (#3).
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci driver.
BUG=b:154756391, b:160651028 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/xhci.c 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43332/3
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43332
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci driver.
BUG=b:154756391 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/xhci.c 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43332/4
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43332/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43332/2//COMMIT_MSG@12 PS2, Line 12: BUG=b:154756391
Can you please add b:160651028 as well?
Done
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43332
to look at the new patch set (#5).
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci driver.
BUG=b:154756391, b:160651028 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/xhci.c 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43332/5
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 5: Code-Review+2
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43332
to look at the new patch set (#6).
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci driver.
BUG=b:154756391, b:160651028 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/xhci.c 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43332/6
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 6:
PTAL, fixed merge conflict
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
Patch Set 6: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43332 )
Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ......................................................................
soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci driver.
BUG=b:154756391, b:160651028 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/xhci.c 3 files changed, 58 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 87d8c51..3bdaad2 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -18,6 +18,7 @@ select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES select DRIVERS_I2C_DESIGNWARE + select DRIVERS_USB_PCI_XHCI select GENERIC_GPIO_LIB select IDT_IN_EVERY_STAGE select IOAPIC diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 203adb5..823d933 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -78,6 +78,7 @@ ramstage-y += update_microcode.c ramstage-y += graphics.c ramstage-y += pcie_gpp.c +ramstage-y += xhci.c
smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c new file mode 100644 index 0000000..171002c --- /dev/null +++ b/src/soc/amd/picasso/xhci.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/gpio_banks.h> +#include <bootstate.h> +#include <device/device.h> +#include <drivers/usb/pci_xhci/pci_xhci.h> +#include <soc/pci_devs.h> +#include <soc/smi.h> +#include <soc/soc_util.h> + +static const struct sci_source xhci_sci_sources[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC1_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + +enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) +{ + if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN) + return CB_ERR_ARG; + + if (dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->path.pci.devfn == XHCI0_DEVFN) + *gpe = xhci_sci_sources[0].gpe; + else if (dev->path.pci.devfn == XHCI1_DEVFN) + *gpe = xhci_sci_sources[1].gpe; + else + return CB_ERR_ARG; + + return CB_SUCCESS; +} + +static void configure_xhci_sci(void *unused) +{ + if (soc_is_reduced_io_sku()) + gpe_configure_sci(xhci_sci_sources, 1); + else + gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources)); +} + + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);
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Aaron Durbin (Code Review) -
Felix Held (Code Review)
-
Furquan Shaikh (Code Review)
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Raul Rangel (Code Review)