Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: x86_64 support ......................................................................
nb/intel/sandybridge: x86_64 support
Add experimental x86_64 support.
Tested on HP Z220: * Still boots on x86_32. * Boots to payload with CB:37395 applied on x86_64.
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smihandler.c 7 files changed, 51 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/1
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..97c8234 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -3,12 +3,20 @@
if CPU_INTEL_MODEL_206AX
+config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select MMX select SSE2 select UDELAY_TSC diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..892b3e3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1957,9 +1957,12 @@ { unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; + uintptr_t addr;
- for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + 4 * j; + write32((void *)addr, j & 2 ? b : a); + }
sfence(); } @@ -1977,13 +1980,16 @@ unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_step = 0x40 * num_of_channels(ctrl); + uintptr_t addr;
- for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); - - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); - + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + j * 4; + write32((void *)addr, 0xffffffff); + } + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + channel_step + j * 4; + write32((void *)addr, 0); + } sfence(); }
@@ -2925,14 +2931,14 @@ if (invert[patno - 1][i] & (1 << (j / 2))) val = ~val;
- write32((void *)((1 << 26) + offset + i * step + j * 4), val); + write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); } } } else { for (i = 0; i < ARRAY_SIZE(pattern); i++) { for (j = 0; j < 16; j++) { const u32 val = pattern[i][j]; - write32((void *)((1 << 26) + offset + i * step + j * 4), val); + write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); } } sfence(); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15be4ab..39d3b66 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -212,7 +212,7 @@ // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2407d92..a108b42 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -265,18 +265,18 @@ { printk(BIOS_DEBUG, "CougarPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); - RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); + RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0)); + RCBA32_AND_OR(CIR5, ~0U, (1 << 0)); + RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR2, ~0U, (1 << 14)); RCBA32(DMC) = 0xc0388400; - RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1)); RCBA32_AND_OR(CIR7, ~0x1f, 0xf); RCBA32(PM_CFG) = 0x050f0000; RCBA32(CIR8) = 0x04000000; - RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); - RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)); + RCBA32_AND_OR(CIR10, ~0U, 0xfffff); + RCBA32_AND_OR(CIR11, ~0U, (1 << 1)); RCBA32(CIR12) = 0x0001c000; RCBA32(CIR14) = 0x00061100; RCBA32(CIR15) = 0x7f8fdfff; @@ -378,10 +378,10 @@ reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16);
- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEB007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEB004000, ~0U, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEC004000, ~0U, (1 << 7));
reg32 = RCBA32(CG); reg32 |= (1 << 31); @@ -672,7 +672,7 @@
/* Add it to DSDT. */ acpigen_write_scope("\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 1c56e5e..7337eae 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -438,7 +438,7 @@ struct me_hfs hfs; u32 reg32;
- mei_base_address = (u32 *) + mei_base_address = (u32 *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 484f0f1..c350186 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -142,7 +142,7 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 7211da3..26b9074 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -96,23 +96,23 @@ case ACPI_S4: /* FIXME: Unbalanced width in read/write ops (16-bit read then 32-bit write) */ reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 &= ~0x03UL; + reg16 &= ~0x03U; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; + xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFU;
/* FIXME: This looks broken (conditions are always false) */ if ((xhci_bar + 0x4C0) & 1) - pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000082, ~0U, (3 << 2)); if ((xhci_bar + 0x4D0) & 1) - pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000182, ~0U, (3 << 2)); if ((xhci_bar + 0x4E0) & 1) - pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000282, ~0U, (3 << 2)); if ((xhci_bar + 0x4F0) & 1) - pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000382, ~0U, (3 << 2));
pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); @@ -192,7 +192,7 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; if (smm_region_overlaps_handler(&r)) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: x86_64 support ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44677/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/44677/1/src/northbridge/intel/sandy... PS1, Line 2934: write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44677/1/src/northbridge/intel/sandy... PS1, Line 2941: write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); line over 96 characters
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: x86_64 support ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44677/1/src/cpu/intel/model_206ax/K... File src/cpu/intel/model_206ax/Kconfig:
https://review.coreboot.org/c/coreboot/+/44677/1/src/cpu/intel/model_206ax/K... PS1, Line 6: ARCH_EXP_X86_64 I guess this breaks the mrc.bin bootpath?
Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44677
to look at the new patch set (#2).
Change subject: nb/intel/sandybridge: x86_64 support ......................................................................
nb/intel/sandybridge: x86_64 support
Add experimental x86_64 support for native raminit. The MRC blobs isn't supported yet as there's no x86_32 wrapper.
Tested on HP Z220: * Still boots on x86_32. * Boots to payload with CB:37395 applied on x86_64.
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smihandler.c 7 files changed, 52 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: x86_64 support ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44677/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/44677/2/src/northbridge/intel/sandy... PS2, Line 2934: write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44677/2/src/northbridge/intel/sandy... PS2, Line 2941: write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); line over 96 characters
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: x86_64 support ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44677/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44677/2//COMMIT_MSG@7 PS2, Line 7: nb/intel/sandybridge: x86_64 support Please make it a statement.
Add x86_64 support
https://review.coreboot.org/c/coreboot/+/44677/2//COMMIT_MSG@9 PS2, Line 9: Add experimental x86_64 support for native raminit. Please extend this, by describing what had to be done:
… by using compatible types.
https://review.coreboot.org/c/coreboot/+/44677/2//COMMIT_MSG@10 PS2, Line 10: blobs singular: blob
Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44677
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: x86_64 support ......................................................................
nb/intel/sandybridge: x86_64 support
Add experimental x86_64 support for native raminit. The MRC blobs isn't supported yet as there's no x86_32 wrapper.
Tested on HP8200: * Still boots on x86_32. * Hangs in permanent SMM handler (SMM relocation handler works with the same code) The call/jmp to c_handler stops the CPU. Even a RSM in long mode doesn't work any more.
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/sata.c 5 files changed, 40 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/3
Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44677
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
nb/intel/sandybridge: Add x86_64 support
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper.
Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/sata.c 5 files changed, 40 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/4
Attention is currently required from: Paul Menzel. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/44677/comment/1bd29107_462581a1 PS2, Line 7: nb/intel/sandybridge: x86_64 support
Please make it a statement. […]
Done
https://review.coreboot.org/c/coreboot/+/44677/comment/c7a0e8e7_a3bac862 PS2, Line 9: Add experimental x86_64 support for native raminit.
Please extend this, by describing what had to be done: […]
Done
https://review.coreboot.org/c/coreboot/+/44677/comment/da0d2e84_0bae67f6 PS2, Line 10: blobs
singular: blob
Done
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44677
to look at the new patch set (#5).
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
nb/intel/sandybridge: Add x86_64 support
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper.
Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/sata.c 5 files changed, 40 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/5
Attention is currently required from: Patrick Rudolph, Paul Menzel. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44677
to look at the new patch set (#6).
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
nb/intel/sandybridge: Add x86_64 support
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper.
Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/sata.c 5 files changed, 40 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/6
Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
Patch Set 6: Code-Review+1
Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
Patch Set 6: Code-Review+2
Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
Patch Set 6:
(1 comment)
File src/cpu/intel/model_206ax/Kconfig:
https://review.coreboot.org/c/coreboot/+/44677/comment/cf7ff228_68964c04 PS1, Line 6: ARCH_EXP_X86_64
I guess this breaks the mrc. […]
Done, explaining in commit message.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44677 )
Change subject: nb/intel/sandybridge: Add x86_64 support ......................................................................
nb/intel/sandybridge: Add x86_64 support
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper.
Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@mailbox.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/sata.c 5 files changed, 40 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index cf6a907..109b6b5 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -3,9 +3,15 @@
if CPU_INTEL_MODEL_206AX
+config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + depends on USE_NATIVE_RAMINIT + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 62a2139..4b5f2b3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1509,9 +1509,12 @@ { unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64; + uintptr_t addr;
- for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + 4 * j; + write32((void *)addr, j & 2 ? b : a); + }
sfence();
@@ -1531,13 +1534,16 @@ unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64; unsigned int channel_step = 64 * num_of_channels(ctrl); + uintptr_t addr;
- for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); - - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); - + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + j * 4; + write32((void *)addr, 0xffffffff); + } + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + channel_step + j * 4; + write32((void *)addr, 0); + } sfence();
program_wdb_pattern_length(channel, 16); @@ -1929,6 +1935,7 @@ unsigned int i, j; unsigned int offset = get_precedening_channels(ctrl, channel) * 64; unsigned int step = 64 * num_of_channels(ctrl); + uintptr_t addr;
if (patno) { u8 base8 = 0x80 >> ((patno - 1) % 8); @@ -1940,14 +1947,16 @@ if (invert[patno - 1][i] & (1 << (j / 2))) val = ~val;
- write32((void *)((1 << 26) + offset + i * step + j * 4), val); + addr = (1 << 26) + offset + i * step + j * 4; + write32((void *)addr, val); } } } else { for (i = 0; i < ARRAY_SIZE(pattern); i++) { for (j = 0; j < 16; j++) { const u32 val = pattern[i][j]; - write32((void *)((1 << 26) + offset + i * step + j * 4), val); + addr = (1 << 26) + offset + i * step + j * 4; + write32((void *)addr, val); } } sfence(); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index dcb0bb4..1f14c42 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -165,7 +165,7 @@ // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c6b42ea..cc2eb28 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -258,18 +258,18 @@ { printk(BIOS_DEBUG, "CougarPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); - RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); + RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0)); + RCBA32_AND_OR(CIR5, ~0U, (1 << 0)); + RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR2, ~0U, (1 << 14)); RCBA32(DMC) = 0xc0388400; - RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1)); RCBA32_AND_OR(CIR7, ~0x1f, 0xf); RCBA32(PM_CFG) = 0x050f0000; RCBA32(CIR8) = 0x04000000; - RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); - RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)); + RCBA32_AND_OR(CIR10, ~0U, 0xfffff); + RCBA32_AND_OR(CIR11, ~0U, (1 << 1)); RCBA32(CIR12) = 0x0001c000; RCBA32(CIR14) = 0x00061100; RCBA32(CIR15) = 0x7f8fdfff; @@ -371,10 +371,10 @@ reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16);
- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEB007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEB004000, ~0U, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEC004000, ~0U, (1 << 7));
reg32 = RCBA32(CG); reg32 |= (1 << 31); diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index c9bc14c..08a254f 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -126,7 +126,7 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00);
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