Patrick Rudolph has uploaded this change for review.
nb/intel/sandybridge: x86_64 support
Add experimental x86_64 support.
Tested on HP Z220:
* Still boots on x86_32.
* Boots to payload with CB:37395 applied on x86_64.
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/cpu/intel/model_206ax/Kconfig
M src/northbridge/intel/sandybridge/raminit_common.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smihandler.c
7 files changed, 51 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/1
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 1918428..97c8234 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -3,12 +3,20 @@
if CPU_INTEL_MODEL_206AX
+config ARCH_EXP_X86_64
+ bool "Experimental 64bit support"
+ default n
+
config CPU_SPECIFIC_OPTIONS
def_bool y
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
+ select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64
select MMX
select SSE2
select UDELAY_TSC
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 3527c8e..892b3e3 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1957,9 +1957,12 @@
{
unsigned int j;
unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40;
+ uintptr_t addr;
- for (j = 0; j < 16; j++)
- write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
+ for (j = 0; j < 16; j++) {
+ addr = 0x04000000 + channel_offset + 4 * j;
+ write32((void *)addr, j & 2 ? b : a);
+ }
sfence();
}
@@ -1977,13 +1980,16 @@
unsigned int j;
unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40;
unsigned int channel_step = 0x40 * num_of_channels(ctrl);
+ uintptr_t addr;
- for (j = 0; j < 16; j++)
- write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
-
- for (j = 0; j < 16; j++)
- write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0);
-
+ for (j = 0; j < 16; j++) {
+ addr = 0x04000000 + channel_offset + j * 4;
+ write32((void *)addr, 0xffffffff);
+ }
+ for (j = 0; j < 16; j++) {
+ addr = 0x04000000 + channel_offset + channel_step + j * 4;
+ write32((void *)addr, 0);
+ }
sfence();
}
@@ -2925,14 +2931,14 @@
if (invert[patno - 1][i] & (1 << (j / 2)))
val = ~val;
- write32((void *)((1 << 26) + offset + i * step + j * 4), val);
+ write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val);
}
}
} else {
for (i = 0; i < ARRAY_SIZE(pattern); i++) {
for (j = 0; j < 16; j++) {
const u32 val = pattern[i][j];
- write32((void *)((1 << 26) + offset + i * step + j * 4), val);
+ write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val);
}
}
sfence();
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 15be4ab..39d3b66 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -212,7 +212,7 @@
// NOTE this will break as soon as the Azalia get's a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
if (RCBA32(CIR31) & (1 << 31)) {
reg32 = pci_read_config32(dev, 0x120);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 2407d92..a108b42 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -265,18 +265,18 @@
{
printk(BIOS_DEBUG, "CougarPoint PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
- RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0));
- RCBA32_AND_OR(CIR5, ~0UL, (1 << 0));
- RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14));
- RCBA16_AND_OR(CIR2, ~0UL, (1 << 14));
+ RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0));
+ RCBA32_AND_OR(CIR5, ~0U, (1 << 0));
+ RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14));
+ RCBA16_AND_OR(CIR2, ~0U, (1 << 14));
RCBA32(DMC) = 0xc0388400;
- RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18));
- RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1));
+ RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18));
+ RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1));
RCBA32_AND_OR(CIR7, ~0x1f, 0xf);
RCBA32(PM_CFG) = 0x050f0000;
RCBA32(CIR8) = 0x04000000;
- RCBA32_AND_OR(CIR10, ~0UL, 0xfffff);
- RCBA32_AND_OR(CIR11, ~0UL, (1 << 1));
+ RCBA32_AND_OR(CIR10, ~0U, 0xfffff);
+ RCBA32_AND_OR(CIR11, ~0U, (1 << 1));
RCBA32(CIR12) = 0x0001c000;
RCBA32(CIR14) = 0x00061100;
RCBA32(CIR15) = 0x7f8fdfff;
@@ -378,10 +378,10 @@
reg16 |= (1 << 11);
pci_write_config16(dev, GEN_PMCON_1, reg16);
- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
- pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
- pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
- pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+ pch_iobp_update(0xEB007F07, ~0U, (1 << 31));
+ pch_iobp_update(0xEB004000, ~0U, (1 << 7));
+ pch_iobp_update(0xEC007F07, ~0U, (1 << 31));
+ pch_iobp_update(0xEC004000, ~0U, (1 << 7));
reg32 = RCBA32(CG);
reg32 |= (1 << 31);
@@ -672,7 +672,7 @@
/* Add it to DSDT. */
acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs);
acpigen_pop_len();
}
}
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 1c56e5e..7337eae 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -438,7 +438,7 @@
struct me_hfs hfs;
u32 reg32;
- mei_base_address = (u32 *)
+ mei_base_address = (u32 *)(uintptr_t)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 484f0f1..c350186 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -142,7 +142,7 @@
pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */
- abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 7211da3..26b9074 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -96,23 +96,23 @@
case ACPI_S4:
/* FIXME: Unbalanced width in read/write ops (16-bit read then 32-bit write) */
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
- reg16 &= ~0x03UL;
+ reg16 &= ~0x03U;
pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL;
+ xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFU;
/* FIXME: This looks broken (conditions are always false) */
if ((xhci_bar + 0x4C0) & 1)
- pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
+ pch_iobp_update(0xEC000082, ~0U, (3 << 2));
if ((xhci_bar + 0x4D0) & 1)
- pch_iobp_update(0xEC000182, ~0UL, (3 << 2));
+ pch_iobp_update(0xEC000182, ~0U, (3 << 2));
if ((xhci_bar + 0x4E0) & 1)
- pch_iobp_update(0xEC000282, ~0UL, (3 << 2));
+ pch_iobp_update(0xEC000282, ~0U, (3 << 2));
if ((xhci_bar + 0x4F0) & 1)
- pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
+ pch_iobp_update(0xEC000382, ~0U, (3 << 2));
pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND,
~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
@@ -192,7 +192,7 @@
smi_apmc_find_state_save(apm_cnt);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (struct global_nvs *)((u32)state->rbx);
+ gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx);
struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)};
if (smm_region_overlaps_handler(&r)) {
printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
To view, visit change 44677. To unsubscribe, or for help writing mail filters, visit settings.