Change in coreboot[master]: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls
Use code comments in the coreboot style and replace outb/inb.rdtsc calls to use coreboot provided functions.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 --- M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/smbus_spd.c 2 files changed, 118 insertions(+), 99 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38163/1
diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 9ddae38..ac52887 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -14,89 +14,98 @@ */
#include <amdblocks/acpimmio.h> +#include <arch/io.h> +#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> #include <AGESA.h> -#include <amdlib.h> #include <northbridge/amd/agesa/dimmSpd.h>
-/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +/* readSmbusByteData - read a single SPD byte from any offset */ +static int readSmbusByteData(uint16_t iobase, int address, char *buffer, + int offset) { unsigned int status; - UINT64 limit; + unsigned long long limit;
- address |= 1; // set read bit + address |= 1; /* set read bit */ + outb(0xff, iobase); /* clear error status */ + outb(0x1f, iobase + 1); /* clear error status */ + outb(offset, iobase + 3); /* offset in eeprom */ + outb(address, iobase + 4); /* slave address and read bit */ + outb(0x48, iobase + 2); /* read byte command */
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; + /* + * time limit to avoid hanging for unexpected error status + * (should never happen) + */ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; }
- buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; }
-/*----------------------------------------------------------------------------- - * +/* * readSmbusByte - read a single SPD byte from the default offset * this function is faster function readSmbusByteData */ - -static int readSmbusByte (int iobase, int address, char *buffer) +static int readSmbusByte(uint16_t iobase, int address, char *buffer) { unsigned int status; - UINT64 limit; + unsigned long long limit;
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + outb(0xff, iobase + 0); /* clear error status */ + outb(0x44, iobase + 2); /* read command */
- // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; + /* time limit to avoid hanging for unexpected error status*/ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; }
- buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; }
-/*--------------------------------------------------------------------------- - * +/* * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. * Optimization relies on autoincrement to avoid * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +static int readspd(uint16_t iobase, int SmbusSlaveAddress, char *buffer, + int count) { int index, error;
@@ -127,15 +136,16 @@ return 0; }
-static void setupFch (int ioBase) +static void setupFch(uint16_t ioBase) { pm_write16(0x2c, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + /* set SMBus clock to 400 KHz */ + outb(66000000 / 400000 / 4, ioBase + 0x0e); }
int hudson_readSpd(int spdAddress, char *buf, size_t len) { - int ioBase = 0xB00; + uint16_t ioBase = 0xb00; setupFch (ioBase); return readspd (ioBase, spdAddress, buf, len); } diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index 8523db5..ac52887 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -14,90 +14,98 @@ */
#include <amdblocks/acpimmio.h> -#include <console/console.h> +#include <arch/io.h> +#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/device.h> - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> +#include <console/console.h> #include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/pi/dimmSpd.h> +#include <northbridge/amd/agesa/dimmSpd.h>
-/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +/* readSmbusByteData - read a single SPD byte from any offset */ +static int readSmbusByteData(uint16_t iobase, int address, char *buffer, + int offset) { unsigned int status; - UINT64 limit; + unsigned long long limit;
- address |= 1; // set read bit + address |= 1; /* set read bit */ + outb(0xff, iobase); /* clear error status */ + outb(0x1f, iobase + 1); /* clear error status */ + outb(offset, iobase + 3); /* offset in eeprom */ + outb(address, iobase + 4); /* slave address and read bit */ + outb(0x48, iobase + 2); /* read byte command */
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; + /* + * time limit to avoid hanging for unexpected error status + * (should never happen) + */ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; }
- buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; }
-/*----------------------------------------------------------------------------- - * +/* * readSmbusByte - read a single SPD byte from the default offset * this function is faster function readSmbusByteData */ - -static int readSmbusByte (int iobase, int address, char *buffer) +static int readSmbusByte(uint16_t iobase, int address, char *buffer) { unsigned int status; - UINT64 limit; + unsigned long long limit;
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + outb(0xff, iobase + 0); /* clear error status */ + outb(0x44, iobase + 2); /* read command */
- // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; + /* time limit to avoid hanging for unexpected error status*/ + limit = rdtscll() + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + status = inb(iobase); + if (rdtscll() > limit) + break; + /* SMBusInterrupt not set, keep waiting */ + if ((status & 2) == 0) + continue; + /* HostBusy set, keep waiting */ + if ((status & 1) == 1) + continue; break; }
- buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = inb(iobase + 5); + /* check for done with no errors */ + if (status == 2) + status = 0; return status; }
-/*--------------------------------------------------------------------------- - * +/* * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. * Optimization relies on autoincrement to avoid * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Reads 128 bytes in 7-8 ms at 400 KHz. */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +static int readspd(uint16_t iobase, int SmbusSlaveAddress, char *buffer, + int count) { int index, error;
@@ -128,15 +136,16 @@ return 0; }
-static void setupFch (int ioBase) +static void setupFch(uint16_t ioBase) { pm_write16(0x2c, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + /* set SMBus clock to 400 KHz */ + outb(66000000 / 400000 / 4, ioBase + 0x0e); }
int hudson_readSpd(int spdAddress, char *buf, size_t len) { - int ioBase = 0xB00; + uint16_t ioBase = 0xb00; setupFch (ioBase); return readspd (ioBase, spdAddress, buf, len); }
Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls
Use code comments in the coreboot style and replace outb/inb/rdtsc calls to use coreboot provided functions.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 --- M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/smbus_spd.c 2 files changed, 118 insertions(+), 99 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38163/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/agesa/h... PS3, Line 20: /* warning: Porting.h includes an open #pragma pack(1) */ Ok.. What this does is nasty. It changes structs to __packed for the remaining of the headers. If we remove any of these, or change the include order around this, commit has to be verified for binary identity.
Please leave the comment in, but replace Porting.h with AGESA.h. The pragma gets indirectly pulled in from there.
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/pi/huds... PS3, Line 21: /* warning: Porting.h includes an open #pragma pack(1) */ Keep comment
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/pi/huds... PS3, Line 23: #include <northbridge/amd/agesa/dimmSpd.h> pi
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 4:
(10 comments)
https://review.coreboot.org/c/coreboot/+/38163/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38163/4//COMMIT_MSG@9 PS4, Line 9: replace To me, "replace X with Y" is "s/X/Y" in vim-speech. I'd rather say "use coreboot-provided inb/outb/rdtsc"
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/agesa/h... PS3, Line 20: /* warning: Porting.h includes an open #pragma pack(1) */
Ok.. What this does is nasty. It changes structs to __packed for the remaining of the headers. […]
#pragma cursed
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 26: readSmbusByteData These things might need a rename
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 27: int offset) But this still fits in 96 chars?
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 43: limit = rdtscll() + 2000000000 / 10; This is reinventing the wheel, there should be a timer API somewhere.
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 60: if (status == 2) : status = 0; : return status; this could even be:
return status == 2 ? 0 : status;
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 80: { Please pick this up (should be on the previous line)
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 112: printk(BIOS_SPEW, "-------------READING SPD-----------\n"); Good thing nobody sees this by default (I hope)
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 139: ioBase This variable should be lowercase
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
PS4: Am I drunk? I think I see double. Aren't these files basically the same thing?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
PS4:
Am I drunk? I think I see double. […]
cheers :) code style changed.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
PS4:
cheers :) […]
I am saying that src/southbridge/amd/{agesa,pi}/hudson/smbus_spd.c seem to be the same thing.
Hello HAOUAS Elyes, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38163
to look at the new patch set (#5).
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls
Refactor code and comments in the coreboot style and use coreboot-provided outb/inb/rdtsc functions.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 --- M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/smbus_spd.c 2 files changed, 135 insertions(+), 130 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38163/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38163/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/5/src/southbridge/amd/agesa/h... PS5, Line 120: error = smbus_read_byte(iobase, smbus_slave_address, &buffer [index]); space prohibited before open square bracket '['
https://review.coreboot.org/c/coreboot/+/38163/5/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/5/src/southbridge/amd/pi/huds... PS5, Line 120: error = smbus_read_byte(iobase, smbus_slave_address, &buffer [index]); space prohibited before open square bracket '['
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 5:
(12 comments)
https://review.coreboot.org/c/coreboot/+/38163/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38163/4//COMMIT_MSG@9 PS4, Line 9: replace
To me, "replace X with Y" is "s/X/Y" in vim-speech. […]
Done
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/agesa/h... PS3, Line 20: /* warning: Porting.h includes an open #pragma pack(1) */
#pragma cursed
Left a comment and AGESA.h include in the same place where Porting.h was
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 26: readSmbusByteData
These things might need a rename
Did some renaming from FoObAr to foo_bar
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 27: int offset)
But this still fits in 96 chars?
Still, I'm not used to it.
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 43: limit = rdtscll() + 2000000000 / 10;
This is reinventing the wheel, there should be a timer API somewhere.
There is in lib/timer.h. Even the wait_us/ms macro looks pretty nice for this use, however, I'm bad at using conditions in macros.
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 60: if (status == 2) : status = 0; : return status;
this could even be: […]
Done
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 80: {
Please pick this up (should be on the previous line)
Done
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 112: printk(BIOS_SPEW, "-------------READING SPD-----------\n");
Good thing nobody sees this by default (I hope)
It should be in RAM still land available in cbmem
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/agesa/h... PS4, Line 139: ioBase
This variable should be lowercase
Done
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/pi/huds... PS3, Line 21: /* warning: Porting.h includes an open #pragma pack(1) */
Keep comment
Done
https://review.coreboot.org/c/coreboot/+/38163/3/src/southbridge/amd/pi/huds... PS3, Line 23: #include <northbridge/amd/agesa/dimmSpd.h>
pi
Done
https://review.coreboot.org/c/coreboot/+/38163/4/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
PS4:
I am saying that src/southbridge/amd/{agesa,pi}/hudson/smbus_spd.c seem to be the same thing.
yes it is (except the dimmSpd.h include)
Hello HAOUAS Elyes, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38163
to look at the new patch set (#6).
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls
Refactor code and comments in the coreboot style and use coreboot-provided outb/inb/rdtsc functions.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I40919df7d6dfbadd09800c8e689382483ffaca14 --- M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/smbus_spd.c 2 files changed, 135 insertions(+), 130 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38163/6
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38163/6/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/6/src/southbridge/amd/agesa/h... PS6, Line 41: * (should never happen) Should fit on one line.
https://review.coreboot.org/c/coreboot/+/38163/6/src/southbridge/amd/agesa/h... PS6, Line 48: One space.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38163 )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38163/6/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/38163/6/src/southbridge/amd/agesa/h... PS6, Line 64: readSmbusByteData this might need an update
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38163?usp=email )
Change subject: sb/amd/{pi,agesa}/hudson/smbus_spd.c: use coreboot code style and calls ......................................................................
Abandoned
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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HAOUAS Elyes (Code Review)
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Kyösti Mälkki (Code Review)
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Michał Żygowski (Code Review)
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Paul Menzel (Code Review)
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Stefan Reinauer (Code Review)