Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: Update dq/dqs mappings ......................................................................
Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162042254 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43988/1
diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 13269db..343c7db 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only
+romstage-y += memory.c + bootblock-y += gpio.c
ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c new file mode 100644 index 0000000..51359e5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg halvor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 12, 13, 9, 11, 8, 15, 14, }, /* DDR0_DQ0[7:0] */ + { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *(void) +{ + return &halvor_memcfg; +}
Hello Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43988
to look at the new patch set (#2).
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
mb/google/volteer/var/halvor: Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162042254 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43988/2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/halvor/memory.c:
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 57: const struct lpddr4x_cfg *(void) function name is missing : variant_memory_params
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/halvor/memory.c:
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 10: { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ nit: align all the comments
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43988
to look at the new patch set (#3).
Change subject: Update dq/dqs mappings ......................................................................
Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162042254 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43988/3
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43988
to look at the new patch set (#4).
Change subject: Update dq/dqs mappings ......................................................................
Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162042254 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43988/4
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: Update dq/dqs mappings ......................................................................
Patch Set 4: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: Update dq/dqs mappings ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/halvor/memory.c:
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 10: { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */
nit: align all the comments
Ack
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 57: const struct lpddr4x_cfg *(void)
function name is missing : variant_memory_params
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: Update dq/dqs mappings ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43988/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43988/4//COMMIT_MSG@7 PS4, Line 7: Update dq/dqs mappings mb/google/volteer/var/halvor: Update dq/dqs mappings
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Angel Pons, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43988
to look at the new patch set (#5).
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
mb/google/volteer/var/halvor: Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162042254 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43988/5
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 5:
Would you help review the CL? Thank you very much.
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43988/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43988/4//COMMIT_MSG@7 PS4, Line 7: Update dq/dqs mappings
mb/google/volteer/var/halvor: Update dq/dqs mappings
Done
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43988/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43988/5//COMMIT_MSG@11 PS5, Line 11: 162042254 do you have another bug that you use for general halvor bringup? as far as i can tell, this one is specific to a power rail enable signal.
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 5: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43988/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43988/5//COMMIT_MSG@11 PS5, Line 11: 162042254
do you have another bug that you use for general halvor […]
The bug should accurately reflect what's going on. Either a general bring-up (as Caveh asked) or a specific one for the DQ/DQS mappings.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Caveh Jalali, Tim Wawrzynczak, Paul Fagerburg, Angel Pons, Nick Vaccaro, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43988
to look at the new patch set (#6).
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
mb/google/volteer/var/halvor: Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43988/6
Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 6:
(4 comments)
Would you help to review the CL again? Thank you.
https://review.coreboot.org/c/coreboot/+/43988/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43988/4//COMMIT_MSG@7 PS4, Line 7: Update dq/dqs mappings
mb/google/volteer/var/halvor: Update dq/dqs mappings
Done
https://review.coreboot.org/c/coreboot/+/43988/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43988/5//COMMIT_MSG@11 PS5, Line 11: 162042254
The bug should accurately reflect what's going on. […]
I have updated bug:162892573 and uploaded reference document for DQ/DQS mappings in Halvor.
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/halvor/memory.c:
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 10: { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */
nit: align all the comments
Done.
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 57: const struct lpddr4x_cfg *(void)
function name is missing : variant_memory_params
Done.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 6: Code-Review+2
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 6: Code-Review+2
You have 2 unresolved comments on patchset 2. You need to mark these as resolved (not just add the word "done" as a comment) before the CL can be merged.
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
Patch Set 6:
(2 comments)
Patch Set 6: Code-Review+2
You have 2 unresolved comments on patchset 2. You need to mark these as resolved (not just add the word "done" as a comment) before the CL can be merged.
Thanks for advise.
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/halvor/memory.c:
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 10: { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */
Done.
Ack
https://review.coreboot.org/c/coreboot/+/43988/2/src/mainboard/google/voltee... PS2, Line 57: const struct lpddr4x_cfg *(void)
Done.
Ack
Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................
mb/google/volteer/var/halvor: Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43988 Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Paul Fagerburg: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 13269db..343c7db 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only
+romstage-y += memory.c + bootblock-y += gpio.c
ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c new file mode 100644 index 0000000..754c7a0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg halvor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 12, 13, 9, 11, 8, 15, 14, }, /* DDR0_DQ0[7:0] */ + { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &halvor_memcfg; +}
Paul Fagerburg has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/43988 )
Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ......................................................................