Change in coreboot[master]: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log

All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/jasperlake/elog.c
1 file changed, 41 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47183/1

diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c
index 235dc6e..d383924 100644
--- a/src/soc/intel/jasperlake/elog.c
+++ b/src/soc/intel/jasperlake/elog.c
@@ -2,11 +2,14 @@

#include <bootstate.h>
 #include <console/console.h>
-#include <stdint.h>
+#include <device/pci_ops.h>
 #include <elog.h>
 #include <intelblocks/pmclib.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <stdint.h>
+
+#define PCIE_ROOT_PORT_STATUS		0x60

static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 {
@@ -20,6 +23,41 @@
    }
 }

+static void pch_log_rp_wake_source(void)
+{
+	size_t i;
+	struct pme_map {
+		pci_devfn_t devfn;
+		unsigned int wake_source;
+	};
+
+	const struct pme_map pme_map[] = {
+		{ PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 },
+		{ PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 },
+		{ PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 },
+		{ PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 },
+		{ PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 },
+		{ PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 },
+		{ PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 },
+		{ PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 },
+		{ PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 },
+		{ PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 },
+		{ PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 },
+		{ PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
+	};
+
+	for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) {
+		const uint32_t pme_status = pci_s_read_config32(
+			pme_map[i].devfn,
+			PCIE_ROOT_PORT_STATUS);
+
+		if (pme_status == 0xFFFFFFFF || !(pme_status & BIT(16)))
+			continue;
+
+		elog_add_event_wake(pme_map[i].wake_source, 0);
+	}
+}
+
 static void pch_log_wake_source(struct chipset_power_state *ps)
 {
    /* Power Button */
@@ -30,9 +68,9 @@
    if (ps->pm1_sts & RTC_STS)
    	elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);

-	/* PCI Express (TODO: determine wake device) */
+	/* PCI Express */
    if (ps->pm1_sts & PCIEXPWAK_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+		pch_log_rp_wake_source();

/* PME (TODO: determine wake device) */
    if (ps->gpe0_sts[GPE_STD] & PME_STS)

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... 
File src/soc/intel/jasperlake/elog.c:

https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... 
PS1, Line 43: 		{ PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 },
            : 		{ PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 },
            : 		{ PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 },
            : 		{ PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
Nit: JSL has only 8 PCIe root ports. I see that the condition in line 49 ensures that that. But felt like this can be removed.

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... 
File src/soc/intel/jasperlake/elog.c:

https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... 
PS1, Line 43: 		{ PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 },
            : 		{ PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 },
            : 		{ PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 },
            : 		{ PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
> Nit: JSL has only 8 PCIe root ports. I see that the condition in line 49 ensures that that. […]

They're defined in soc/pci_devs.h as the first four functions in 00:1d; maybe a different processor SKU could have them and then the mainboard would only need to change the Kconfig.

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... 
File src/soc/intel/jasperlake/elog.c:

https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... 
PS1, Line 43: 		{ PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 },
            : 		{ PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 },
            : 		{ PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 },
            : 		{ PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
> They're defined in soc/pci_devs. […]

If I am not wrong, it was a copy-paste error while copying from TGL. Anyways we can deal with that in a separate CL.

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47183

to look at the new patch set (#2).

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log

All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/jasperlake/elog.c
1 file changed, 38 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47183/2

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47183

to look at the new patch set (#3).

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log

All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/jasperlake/elog.c
1 file changed, 33 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47183/3

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded a new patch set (#4) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log

All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/jasperlake/elog.c
1 file changed, 33 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47183/4

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47183

to look at the new patch set (#5).

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log

All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/jasperlake/elog.c
1 file changed, 38 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47183/5

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

Patch Set 5: Code-Review+2

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

Patch Set 5: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47183 )

Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
......................................................................

soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log

All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47183
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Karthik Ramasubramanian 
---
M src/soc/intel/jasperlake/elog.c
1 file changed, 38 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c
index 235dc6e..0546bb0 100644
--- a/src/soc/intel/jasperlake/elog.c
+++ b/src/soc/intel/jasperlake/elog.c
@@ -2,11 +2,13 @@

#include <bootstate.h>
 #include <console/console.h>
-#include <stdint.h>
+#include <device/pci_ops.h>
 #include <elog.h>
 #include <intelblocks/pmclib.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <stdint.h>
+#include <types.h>

static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 {
@@ -20,6 +22,39 @@
    }
 }

+static void pch_log_rp_wake_source(void)
+{
+	size_t i;
+	struct pme_map {
+		pci_devfn_t devfn;
+		unsigned int wake_source;
+	};
+
+	const struct pme_map pme_map[] = {
+		{ PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 },
+		{ PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 },
+		{ PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 },
+		{ PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 },
+		{ PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 },
+		{ PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 },
+		{ PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 },
+		{ PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 },
+		{ PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 },
+		{ PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 },
+		{ PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 },
+		{ PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
+	};
+
+	for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) {
+		const struct device *dev = pcidev_path_on_root(pme_map[i].devfn);
+		if (!dev)
+			continue;
+
+		if (pci_dev_is_wake_source(dev))
+			elog_add_event_wake(pme_map[i].wake_source, 0);
+	}
+}
+
 static void pch_log_wake_source(struct chipset_power_state *ps)
 {
    /* Power Button */
@@ -30,9 +65,9 @@
    if (ps->pm1_sts & RTC_STS)
    	elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);

-	/* PCI Express (TODO: determine wake device) */
+	/* PCI Express */
    if (ps->pm1_sts & PCIEXPWAK_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+		pch_log_rp_wake_source();

/* PME (TODO: determine wake device) */
    if (ps->gpe0_sts[GPE_STD] & PME_STS)