1 comment:
File src/soc/intel/jasperlake/elog.c:
{ PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 },
{ PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 },
{ PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 },
{ PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
Nit: JSL has only 8 PCIe root ports. I see that the condition in line 49 ensures that that. […]
They're defined in soc/pci_devs.h as the first four functions in 00:1d; maybe a different processor SKU could have them and then the mainboard would only need to change the Kconfig.
To view, visit change 47183. To unsubscribe, or for help writing mail filters, visit settings.