Name of user not set #1003058 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 481 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/1
diff --git a/src/mainboard/lenovo/thinkcentre_m91p/Kconfig b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig new file mode 100644 index 0000000..07fc6cf --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig @@ -0,0 +1,32 @@ +if BOARD_LENOVO_THINKCENTRE_M91P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select MAINBOARD_USES_IFD_GBE_REGION + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default lenovo/thinkcentre_m91p + +config MAINBOARD_PART_NUMBER + string + default "ThinkCentre M91p" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 10 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name new file mode 100644 index 0000000..01956a6 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKCENTRE_M91P + bool "ThinkCentre M91p" diff --git a/src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc b/src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl b/src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl new file mode 100644 index 0000000..afb8abb --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c new file mode 100644 index 0000000..f8364ab --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/board_info.txt b/src/mainboard/lenovo/thinkcentre_m91p/board_info.txt new file mode 100644 index 0000000..3353f8d --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/board_info.txt @@ -0,0 +1,2 @@ +Category: desktop +FIXME: check category, , put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/lenovo/thinkcentre_m91p/data.vbt b/src/mainboard/lenovo/thinkcentre_m91p/data.vbt new file mode 100644 index 0000000..73336f72 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb new file mode 100644 index 0000000..7a7da62 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb @@ -0,0 +1,105 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x8" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x0" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x3070 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x3070 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x3070 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x17aa 0x3070 + end + device pci 1c.0 off # PCIe Port #1 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x3070 + end + device pci 1e.0 on # PCI bridge + subsystemid 0x17aa 0x3070 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x17aa 0x3070 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x3070 + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x3070 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x3070 + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x17aa 0x3070 + end + end +end diff --git a/src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl b/src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl new file mode 100644 index 0000000..e648a99 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl @@ -0,0 +1,28 @@ +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/early_init.c b/src/mainboard/lenovo/thinkcentre_m91p/early_init.c new file mode 100644 index 0000000..e3facd4 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/early_init.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <device/pci.h> +#include <device/pci_def.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads new file mode 100644 index 0000000..df757d1 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/thinkcentre_m91p/gpio.c b/src/mainboard/lenovo/thinkcentre_m91p/gpio.c new file mode 100644 index 0000000..fc6b035 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/gpio.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c b/src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c new file mode 100644 index 0000000..6786be0 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ + 0x17aa3070, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa3070), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x99130120), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x17aa3070, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x17aa3070), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/thinkcentre_m91p/mainboard.c b/src/mainboard/lenovo/thinkcentre_m91p/mainboard.c new file mode 100644 index 0000000..e5cfebf --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/mainboard.c @@ -0,0 +1,15 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 1:
(12 comments)
Welcome!
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 9: /* The lid is open by default. */ : gnvs->lids = 1; Which lid? This isn't a laptop, so this can be dropped.
You can then drop the FIXME above as well.
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 1: # FIXME: GPU registers may not always apply. : register "gfx" = "GMA_STATIC_DISPLAYS(0)" : register "gpu_cpu_backlight" = "0x00000000" : register "gpu_dp_b_hotplug" = "0" : register "gpu_dp_c_hotplug" = "0" : register "gpu_dp_d_hotplug" = "0" : register "gpu_panel_port_select" = "0" : register "gpu_panel_power_backlight_off_delay" = "0" : register "gpu_panel_power_backlight_on_delay" = "0" : register "gpu_panel_power_cycle_delay" = "0" : register "gpu_panel_power_down_delay" = "0" : register "gpu_panel_power_up_delay" = "0" : register "gpu_pch_backlight" = "0x00000000" This can be dropped completely (starting from the FIXME up until `gpu_pch_backlight` (inclusive).
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 23: end nit: I usually `pick up` these lone `end` keywords and put them on the same line if there's nothing inside the corresponding `device`:
device lapic 0x0 on end device lapic 0xacac off end
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 31: register "docking_supported" = "0" Any devicetree field that is zero and does not provide any useful info can be removed. For example, this.
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 33: register "gen2_dec" = "0x00000000" : register "gen3_dec" = "0x00000000" : register "gen4_dec" = "0x00000000" : register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" Also zero, can be dropped
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 60: device pci 1c.0 off # PCIe Port #1 : end : device pci 1c.1 off # PCIe Port #2 : end : device pci 1c.2 off # PCIe Port #3 : end : device pci 1c.3 off # PCIe Port #4 : end : device pci 1c.4 off # PCIe Port #5 : end : device pci 1c.5 off # PCIe Port #6 : end : device pci 1c.6 off # PCIe Port #7 : end : device pci 1c.7 off # PCIe Port #8 : end this is weird.
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 96: Host bridge Host bridge One `Host bridge` is enough, isn't it? 😄
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 96: device pci 00.0 on # Host bridge Host bridge : subsystemid 0x17aa 0x3070 : end : device pci 01.0 off # PEG : end : device pci 02.0 on # iGPU : subsystemid 0x17aa 0x3070 : end These devices correspond to northbridge functions. I prefer to have them above the southbridge (that is, just before `chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH`)
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 1: #define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB : #define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB These definitions are unused and can be removed.
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 25: #include <drivers/intel/gma/acpi/default_brightness_levels.asl> No backlight on this board, so this isn't necessary.
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/early_init.c:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 3: nit: double blank line
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 33: /* FIXME: Put proper SPD map here. */ Easy way to test: check if the board is able to boot with a single DIMM, for every slot. Especially interesting are the two middle slots.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#2).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 444 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#3).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 438 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/3
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#4).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 437 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/4
Name of user not set #1003058 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 4:
(11 comments)
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 9: /* The lid is open by default. */ : gnvs->lids = 1;
Which lid? This isn't a laptop, so this can be dropped. […]
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 1: # FIXME: GPU registers may not always apply. : register "gfx" = "GMA_STATIC_DISPLAYS(0)" : register "gpu_cpu_backlight" = "0x00000000" : register "gpu_dp_b_hotplug" = "0" : register "gpu_dp_c_hotplug" = "0" : register "gpu_dp_d_hotplug" = "0" : register "gpu_panel_port_select" = "0" : register "gpu_panel_power_backlight_off_delay" = "0" : register "gpu_panel_power_backlight_on_delay" = "0" : register "gpu_panel_power_cycle_delay" = "0" : register "gpu_panel_power_down_delay" = "0" : register "gpu_panel_power_up_delay" = "0" : register "gpu_pch_backlight" = "0x00000000"
This can be dropped completely (starting from the FIXME up until `gpu_pch_backlight` (inclusive).
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 23: end
nit: I usually `pick up` these lone `end` keywords and put them on the same line if there's nothing […]
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 31: register "docking_supported" = "0"
Any devicetree field that is zero and does not provide any useful info can be removed. […]
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 33: register "gen2_dec" = "0x00000000" : register "gen3_dec" = "0x00000000" : register "gen4_dec" = "0x00000000" : register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
Also zero, can be dropped
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 60: device pci 1c.0 off # PCIe Port #1 : end : device pci 1c.1 off # PCIe Port #2 : end : device pci 1c.2 off # PCIe Port #3 : end : device pci 1c.3 off # PCIe Port #4 : end : device pci 1c.4 off # PCIe Port #5 : end : device pci 1c.5 off # PCIe Port #6 : end : device pci 1c.6 off # PCIe Port #7 : end : device pci 1c.7 off # PCIe Port #8 : end
this is weird.
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 96: Host bridge Host bridge
One `Host bridge` is enough, isn't it? 😄
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 96: device pci 00.0 on # Host bridge Host bridge : subsystemid 0x17aa 0x3070 : end : device pci 01.0 off # PEG : end : device pci 02.0 on # iGPU : subsystemid 0x17aa 0x3070 : end
These devices correspond to northbridge functions. […]
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 1: #define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB : #define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB
These definitions are unused and can be removed.
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 25: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
No backlight on this board, so this isn't necessary.
Done
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/early_init.c:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 3:
nit: double blank line
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#5).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 437 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/5
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#6).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 437 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 60: device pci 1c.0 off # PCIe Port #1 : end : device pci 1c.1 off # PCIe Port #2 : end : device pci 1c.2 off # PCIe Port #3 : end : device pci 1c.3 off # PCIe Port #4 : end : device pci 1c.4 off # PCIe Port #5 : end : device pci 1c.5 off # PCIe Port #6 : end : device pci 1c.6 off # PCIe Port #7 : end : device pci 1c.7 off # PCIe Port #8 : end
Done
No, what I meant is that the mainboard has PCIe slots, so that they are disabled is weird. I'll comment on the latest patchset according to schematics
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... PS5, Line 16: device domain 0x0 on Since the subsystem ID is the same everywhere, you can remove all `subsystemid` lines and put this here:
subsystemid 0x17aa 0x3070 inherit
Saves some redundancy 😄
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... PS5, Line 20: end This is part of the comment (comments begin with `#` in the devicetree), so it most likely doesn't build. It should be:
device pci 01.0 off end # PEG
And actually, it should be on: this is the PCIe x16 slot.
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... PS5, Line 45: device pci 1c.0 off # PCIe Port #1 end We need to keep unused root ports here, otherwise they will be enabled. According to schematics:
device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 on end # PCIe Port #5 - PCIe x1 slot device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#7).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 416 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44302/7/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44302/7/src/mainboard/lenovo/thinkc... PS7, Line 28: device pci 16.1 off end # Management Engine Interface 2 trailing whitespace
https://review.coreboot.org/c/coreboot/+/44302/7/src/mainboard/lenovo/thinkc... PS7, Line 29: device pci 16.2 off end # Management Engine IDE-R trailing whitespace
https://review.coreboot.org/c/coreboot/+/44302/7/src/mainboard/lenovo/thinkc... PS7, Line 30: device pci 16.3 off end # Management Engine KT trailing whitespace
https://review.coreboot.org/c/coreboot/+/44302/7/src/mainboard/lenovo/thinkc... PS7, Line 31: device pci 19.0 on end # Intel Gigabit Ethernet trailing whitespace
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#8).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 416 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#9).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 424 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#10).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 424 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/10
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#11).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 423 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 11:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... PS5, Line 16: device domain 0x0 on
Since the subsystem ID is the same everywhere, you can remove all `subsystemid` lines and put this h […]
Done
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... PS5, Line 20: end
This is part of the comment (comments begin with `#` in the devicetree), so it most likely doesn't b […]
should be on
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... PS5, Line 45: device pci 1c.0 off # PCIe Port #1 end
We need to keep unused root ports here, otherwise they will be enabled. According to schematics: […]
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#12).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 423 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/12
Name of user not set #1003058 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44302/5/src/mainboard/lenovo/thinkc... PS5, Line 20: end
should be on
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44302/12/src/mainboard/lenovo/think... File src/mainboard/lenovo/thinkcentre_m91p/Kconfig:
https://review.coreboot.org/c/coreboot/+/44302/12/src/mainboard/lenovo/think... PS12, Line 25: config DRAM_RESET_GATE_GPIO # FIXME: check this : int : default 10 This is wrong. There's no reset gate on this board, you can use GPIO72 instead. But please leave a comment:
# Board has no DRAM reset gate GPIO, and GPIO72 is unused.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... File src/mainboard/lenovo/thinkcentre_m91p/early_init.c:
https://review.coreboot.org/c/coreboot/+/44302/1/src/mainboard/lenovo/thinkc... PS1, Line 33: /* FIXME: Put proper SPD map here. */
Easy way to test: check if the board is able to boot with a single DIMM, for every slot. […]
See latest patchset.
https://review.coreboot.org/c/coreboot/+/44302/12/src/mainboard/lenovo/think... File src/mainboard/lenovo/thinkcentre_m91p/early_init.c:
https://review.coreboot.org/c/coreboot/+/44302/12/src/mainboard/lenovo/think... PS12, Line 36: read_spd(&spd[1], 0x52, id_only); : read_spd(&spd[2], 0x51, id_only); The SPD addresses for these two are swapped, and should be:
read_spd(&spd[1], 0x51, id_only); read_spd(&spd[2], 0x52, id_only);
Easy way to test: check if the board is able to boot with a single DIMM, for every slot. Especially interesting are the two middle slots.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44302
to look at the new patch set (#13).
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip
Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom
Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE
Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 bengrisdale123@gmail.com Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 420 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/13
Name of user not set #1003058 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44302/12/src/mainboard/lenovo/think... File src/mainboard/lenovo/thinkcentre_m91p/early_init.c:
https://review.coreboot.org/c/coreboot/+/44302/12/src/mainboard/lenovo/think... PS12, Line 36: read_spd(&spd[1], 0x52, id_only); : read_spd(&spd[2], 0x51, id_only);
The SPD addresses for these two are swapped, and should be: […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44302 )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Patch Set 13:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44302/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44302/13//COMMIT_MSG@7 PS13, Line 7: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p Please add a colon after the prefix.
https://review.coreboot.org/c/coreboot/+/44302/13//COMMIT_MSG@10 PS13, Line 10: This is an OEM board with a Macronix MX25L6406E flash chip 1. Please add dots at the end of sentences. 2. Please mention what chipset/socket this mainboard has.
https://review.coreboot.org/c/coreboot/+/44302/13//COMMIT_MSG@13 PS13, Line 13: - All DIMM slots Do you know the DIMM model?
https://review.coreboot.org/c/coreboot/+/44302/13//COMMIT_MSG@21 PS13, Line 21: SATA Ports SATA ports
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44302?usp=email )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
Felix Singer has restored this change. ( https://review.coreboot.org/c/coreboot/+/44302?usp=email )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Restored
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44302?usp=email )
Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ......................................................................
Abandoned
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
-
Felix Singer (Code Review)
-
Martin L Roth (Code Review)
-
Name of user not set (Code Review)
-
Paul Menzel (Code Review)