Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37164 )
Change subject: cpu/intel/slot_1: Cache romstage XIP execution ......................................................................
cpu/intel/slot_1: Cache romstage XIP execution
Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/slot_1/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37164/1
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 7919974..a8d90e8 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,6 +27,7 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select SETUP_XIP_CACHE
config DCACHE_RAM_BASE hex
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37164 )
Change subject: cpu/intel/slot_1: Cache romstage XIP execution ......................................................................
Patch Set 4: Code-Review+1
This patch mitigated the 1.5s slowdown on asus/p2b-ls.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37164 )
Change subject: cpu/intel/slot_1: Cache romstage XIP execution ......................................................................
Patch Set 5: Code-Review+2
It works? Nice!
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37164 )
Change subject: cpu/intel/slot_1: Cache romstage XIP execution ......................................................................
cpu/intel/slot_1: Cache romstage XIP execution
Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/37164 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Keith Hui buurin@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/slot_1/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Keith Hui: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 7919974..a8d90e8 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,6 +27,7 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select SETUP_XIP_CACHE
config DCACHE_RAM_BASE hex
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Keith Hui (Code Review)
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Patrick Georgi (Code Review)