Arthur Heymans has uploaded this change for review.

View Change

cpu/intel/slot_1: Cache romstage XIP execution

Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/cpu/intel/slot_1/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37164/1

diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 7919974..a8d90e8 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -27,6 +27,7 @@
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
+	select SETUP_XIP_CACHE
 
 config DCACHE_RAM_BASE
 	hex

To view, visit change 37164. To unsubscribe, or for help writing mail filters, visit settings.