Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl 1 file changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/1
diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl new file mode 100644 index 0000000..4a981b7 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +#include <soc/gpio.h> + +#define GPIOTXSTATE_MASK 0x1 +#define GPIORXSTATE_MASK 0x1 + +Device (GPIO) +{ + Name (_HID, "INT3536") + Name (_UID, 1) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { 0 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + Store (^^PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + Store (^^PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + Store (^^PCRB (PID_GPIOCOM3), BAS3) + Store (GPIO_BASE_SIZE, LEN3) + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + Store (^^PCRB (PID_GPIOCOM4), BAS4) + Store (GPIO_BASE_SIZE, LEN4) + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + Store (^^PCRB (PID_GPIOCOM5), BAS5) + Store (GPIO_BASE_SIZE, LEN5) + + CreateDWordField (^RBUF, ^GIRQ._INT, IRQN) + And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG), + GPIO_DRIVER_IRQ_ROUTE_MASK, Local0) + + /* TODO: Check this! + If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { + Store (GPIO_IRQ14, IRQN) + } Else { + Store (GPIO_IRQ15, IRQN) + } + */ + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_F23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 3 */ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_I0, Local1) + } + /* GPIO Community 4 */ + If (LAnd (LGreaterEqual (Arg0, GPP_J0), LLessEqual (Arg0, GPP_K10))) + { + Store (PID_GPIOCOM4, Local0) + Subtract (Arg0, GPP_J0, Local1) + } + /* GPIO Community 5 */ + If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_L19))) + { + Store (PID_GPIOCOM5, Local0) + Subtract (Arg0, GPP_G0, Local1) + } + Store (PCRB (Local0), Local2) + Add (Local2, PAD_CFG_BASE, Local2) + Return (Add (Local2, Multiply (Local1, 8))) +} + +/* + * Get GPIO Rx Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (GPIOTXSTATE_MASK, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) +}
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/2
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/10
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#17).
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 166 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/17
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#18).
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 166 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/18
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#20).
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 165 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/20
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#24).
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 165 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/24
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#26).
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 165 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/26
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#33).
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 165 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/33
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#34).
Change subject: [WIP] intel/xeon_sp: add ACPI to control GPIO ......................................................................
[WIP] intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 139 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/34
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#35).
Change subject: [WIP] intel/xeon_sp: add ACPI to control GPIO ......................................................................
[WIP] intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h 2 files changed, 139 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/35
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#37).
Change subject: [WIP] intel/xeon_sp: add ACPI to control GPIO ......................................................................
[WIP] intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/37
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#38).
Change subject: [WIP] intel/xeon_sp: add ACPI to control GPIO ......................................................................
[WIP] intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/deltalake/dsdt.asl A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 148 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/38
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Andrey Petrov, Jonathan Zhang, Johnny Lin, Morgan Jang, Patrick Rudolph,
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to look at the new patch set (#39).
Change subject: [WIP] intel/xeon_sp: add ACPI to control GPIO ......................................................................
[WIP] intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 145 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/39
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#40).
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 145 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/40
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 40:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39979/40/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/40/src/soc/intel/xeon_sp/acpi... PS40, Line 126: Case (COMM_2) { : Local0 = PID_GPIOCOM2 Community 3? Actually Community 2 is listed in EDS. But we would better to follow implementation in kernel.
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#41).
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 145 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/41
Attention is currently required from: Lance Zhao. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41:
(1 comment)
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/34355021_5463efff PS40, Line 126: Case (COMM_2) { : Local0 = PID_GPIOCOM2
Community 3? Actually Community 2 is listed in EDS. […]
Do you mean the order of the communities in the pincntr driver?
https://github.com/torvalds/linux/blob/master/drivers/pinctrl/intel/pinctrl-... static const struct intel_community lbg_communities[] = { LBG_COMMUNITY(0, 0, 71), LBG_COMMUNITY(1, 72, 132), LBG_COMMUNITY(3, 133, 144), LBG_COMMUNITY(4, 145, 180), LBG_COMMUNITY(5, 181, 246), };
Attention is currently required from: Maxim Polyakov. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41: Code-Review+2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41:
(1 comment)
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/7dfd107e_1ae15edb PS40, Line 126: Case (COMM_2) { : Local0 = PID_GPIOCOM2
Do you mean the order of the communities in the pincntr driver? […]
Ack
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41:
(1 comment)
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/ba616481_a27ee4b0 PS40, Line 126: Case (COMM_2) { : Local0 = PID_GPIOCOM2
Ack
Thanks for the review
Attention is currently required from: Maxim Polyakov. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41:
(1 comment)
Patchset:
PS41: This needs to be tested first. Maxim, do you have any specific test procedures in mind?
Attention is currently required from: Maxim Polyakov. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41: -Code-Review
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/39979/comment/3ee1cdb1_6a5969b9 PS41, Line 8: The commit message does not follow community's guide line, hence take back my +2.
Attention is currently required from: Jonathan Zhang, Maxim Polyakov, Jingle Hsu. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41:
(1 comment)
Patchset:
PS41:
This needs to be tested first. […]
A proper test step will be trying to toggle gpio pin from sysfs to see that's functional or not. Though current change didn't touch any platform level.
Attention is currently required from: Jonathan Zhang, Maxim Polyakov. Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41:
(2 comments)
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/a3012dc4_0337fd2d PS41, Line 19: Memory32Fixed (ReadWrite, 0, 0, COM1) When resource/_CRS not for com2, boot message shows (lewisburg-pinctrl INT3536:00: invalid resource). (kernel 4.18.0)
https://review.coreboot.org/c/coreboot/+/39979/comment/4fc26a68_e4ace1a0 PS41, Line 82: GPP_H23 Out of community 1 range.
Attention is currently required from: Jonathan Zhang, Maxim Polyakov. Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 41:
(1 comment)
Patchset:
PS41: In path /sys/kernel/debug/pinctrl/ ,can't see controller.
Attention is currently required from: Jonathan Zhang, Maxim Polyakov. Hello Lance Zhao, build bot (Jenkins), Lijian Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Andrey Petrov, Jonathan Zhang, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39979
to look at the new patch set (#42).
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 179 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/42
Attention is currently required from: Jonathan Zhang, Jingle Hsu. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 43:
(3 comments)
Patchset:
PS43: Thanks for review and testing
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/70b96c94_e7d6ab94 PS41, Line 19: Memory32Fixed (ReadWrite, 0, 0, COM1)
When resource/_CRS not for com2, […]
COM2 has been added in the patch-set 42.
https://review.coreboot.org/c/coreboot/+/39979/comment/e9a3a74b_054746e0 PS41, Line 82: GPP_H23
Out of community 1 range.
Done
Attention is currently required from: Jonathan Zhang, Jingle Hsu. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 43:
(1 comment)
Patchset:
PS41:
In path /sys/kernel/debug/pinctrl/ ,can't see controller.
When I use AMI, I can see there
sudo ls /sys/kernel/debug/pinctrl/ pinctrl-devices pinctrl-handles pinctrl-maps
So, if I understand correctly, /sys/kernel/debug/pinctrl doesn't exist in the case of coreboot, is it right?
Attention is currently required from: Maxim Polyakov, Jingle Hsu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 43:
(1 comment)
Patchset:
PS41:
When I use AMI, I can see there […]
Is it because CONFIG_PINCTRL needs to be set for target OS?
Attention is currently required from: Jonathan Zhang, Maxim Polyakov. Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 43:
(1 comment)
Patchset:
PS41:
Is it because CONFIG_PINCTRL needs to be set for target OS?
What I meant is that the controller file is not created: /sys/kernel/debug/pinctrl/INT3536:00, but with patch set 43 I can see it being created and I can control the GPIO via interface "/sys/class/gpio" now.
Attention is currently required from: Maxim Polyakov. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 43: Code-Review+1
Attention is currently required from: Jonathan Zhang, Maxim Polyakov, Jingle Hsu. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 43:
(2 comments)
Patchset:
PS41:
What I meant is that the controller file is not created: […]
The current kernel is the following, why we need to com2 to be included? Because of calculation?
static const struct intel_community lbg_communities[] = { LBG_COMMUNITY(0, 0, 71), LBG_COMMUNITY(1, 72, 132), LBG_COMMUNITY(3, 133, 144), LBG_COMMUNITY(4, 145, 180), LBG_COMMUNITY(5, 181, 246), };
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/296051c8_990c2353 PS43, Line 13: 1 If we have only one "INT35336" and then _UID is not needed or _UID can be 0.
Attention is currently required from: Jonathan Zhang, Maxim Polyakov, Jingle Hsu. Hello Lance Zhao, build bot (Jenkins), Lijian Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Andrey Petrov, Jonathan Zhang, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39979
to look at the new patch set (#44).
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
intel/xeon_sp: add ACPI to control GPIO
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 179 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/44
Attention is currently required from: Lance Zhao, Jonathan Zhang, Jingle Hsu. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 44:
(2 comments)
Patchset:
PS41:
The current kernel is the following, why we need to com2 to be included? Because of calculation? […]
@Lance, I agree with you, at the beginning I excluded com2 according to this table from the kernel sources, but testing shows that this is necessary.
@Jingle, thanks for testing. I'm glad it finally works, but are you sure about com2? Maybe the problem is in the wrong GPIO Community 1 range only?
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/e81f8a7e_4d7ea4fc PS43, Line 13: 1
If we have only one "INT35336" and then _UID is not needed or _UID can be 0.
Done
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jonathan Zhang. Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 44:
(1 comment)
Patchset:
PS41:
@Lance, I agree with you, at the beginning I excluded com2 according to this table from the kernel s […] Maybe the problem is in the wrong GPIO Community 1 range only?
Base on patch set 41, modify community 1 range only, Target OS (5.3.0) message as below [ 1.091009] pinctrl core: initialized pinctrl subsystem [ 2.868186] lewisburg-pinctrl INT3536:00: invalid resource [ 2.879206] lewisburg-pinctrl: probe of INT3536:00 failed with error -22 Cannot control gpio via /sys/class/gpio. Root cause need to check.
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jonathan Zhang. Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: add ACPI to control GPIO ......................................................................
Patch Set 44:
(1 comment)
Patchset:
PS41:
Maybe the problem is in the wrong GPIO Community 1 range only? […]
There is a mapping in Linux between resource array and barNo. In drivers/base/platform.c platform_get_resource(), it would look for the resource by the array index from the parameter 'unsigned int num'. Resource array is declared as ResourceTemplate in gpio.asl. barNo is the index of the resource to be returned.
In this case: LBG_COMMUNITY(5, 181, 246), kernel will look for resource through array index 5, if we don't add COM2 to ResourceTemplate(), it will got the wrong resouce 'Interrupt' which causes returning error of invalid resource.
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jonathan Zhang. Hello Lance Zhao, build bot (Jenkins), Lijian Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Andrey Petrov, Jonathan Zhang, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39979
to look at the new patch set (#45).
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
intel/xeon_sp: Add ACPI to control GPIO
This has been tested on the OCP Delta Lake platform.
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 179 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/45
Attention is currently required from: Lance Zhao, Jonathan Zhang, Jingle Hsu. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 46:
(1 comment)
Patchset:
PS41:
There is a mapping in Linux between resource array and barNo. […]
Hi Jingle! I'm sorry for not writing for a long time and thank you so much for the detailed explanation. I think we can mark this as resolved.
@Jonathan, @Lance, Do you have any other comments? Can we add this to the master?
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jingle Hsu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 46:
(1 comment)
Patchset:
PS41:
Hi Jingle! I'm sorry for not writing for a long time and thank you so much for the detailed explanat […]
Hi Maxim, Jingle and team will come back from Chinese New Year holiday mid next week. We will take care of this PR shortly after that. Thanks!
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jingle Hsu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 46: Code-Review+1
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jingle Hsu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 46: Code-Review+2
Attention is currently required from: Lance Zhao, Jingle Hsu. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 46:
(2 comments)
Patchset:
PS46: Thanks for the review and help with this work!
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/213a2e2f_6693c6b0 PS41, Line 19: Memory32Fixed (ReadWrite, 0, 0, COM1)
COM2 has been added in the patch-set 42.
Ack
Attention is currently required from: Lance Zhao, Jingle Hsu. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 46:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/39979/comment/29a24192_a422f1ee PS41, Line 8:
The commit message does not follow community's guide line, hence take back my +2.
Ack
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jingle Hsu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 46: Code-Review+1
(1 comment)
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/a38fefdf_8995f815 PS46, Line 69: resourse typo: resour*c*e
Attention is currently required from: Lance Zhao, Maxim Polyakov, Jingle Hsu. Hello Lance Zhao, build bot (Jenkins), Lijian Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Andrey Petrov, Jonathan Zhang, Johnny Lin, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39979
to look at the new patch set (#47).
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
intel/xeon_sp: Add ACPI to control GPIO
This has been tested on the OCP Delta Lake platform.
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 179 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/47
Attention is currently required from: Lance Zhao, Jingle Hsu, Angel Pons. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 47:
(1 comment)
File src/soc/intel/xeon_sp/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39979/comment/c24db6d8_554b0219 PS46, Line 69: resourse
typo: resour*c*e
Thx Done
Attention is currently required from: Maxim Polyakov, Jingle Hsu, Angel Pons. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
Patch Set 47: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: intel/xeon_sp: Add ACPI to control GPIO ......................................................................
intel/xeon_sp: Add ACPI to control GPIO
This has been tested on the OCP Delta Lake platform.
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lance Zhao --- A src/soc/intel/xeon_sp/acpi/gpio.asl M src/soc/intel/xeon_sp/acpi/pch.asl M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/irq.h 4 files changed, 179 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl new file mode 100644 index 0000000..6fe3d51 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <soc/gpio.h> +#include <soc/pcr_ids.h> +#include <soc/irq.h> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> +#include <soc/intel/common/acpi/pcr.asl> + +Device (GPIO) +{ + Name (_HID, "INT3536") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { PCH_IRQ14 } + }) + + /* Current Resource Settings */ + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + /* Return status of power resource */ + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + if ((Arg0 >= GPP_A0) && (Arg0 <= GPP_F23)) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_A0 + } + + /* GPIO Community 1 */ + if ((Arg0 >= GPP_C0) && (Arg0 <= GPP_E12)) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_C0 + } + + /* GPIO Community 2 */ + if ((Arg0 >= GPD0) && (Arg0 <= GPD11)) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPD0 + } + + /* GPIO Community 3 */ + if ((Arg0 >= GPP_I0) && (Arg0 <= GPP_I10)) + { + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPP_I0 + } + + /* GPIO Community 4 */ + if ((Arg0 >= GPP_J0) && (Arg0 <= GPP_K10)) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPP_J0 + } + + /* GPIO Community 5 */ + if ((Arg0 >= GPP_G0) && (Arg0 <= GPP_L19)) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPP_G0 + } + + Local2 = PCRB (Local0) + Local2 += PAD_CFG_BASE + Return (Local2 + (Local1 * 8)) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) + { + Local0 = PID_GPIOCOM0 + } + + Case (COMM_1) + { + Local0 = PID_GPIOCOM1 + } + + Case (COMM_2) + { + Local0 = PID_GPIOCOM2 + } + + Case (COMM_3) + { + Local0 = PID_GPIOCOM3 + } + + Case (COMM_4) + { + Local0 = PID_GPIOCOM4 + } + + Case (COMM_5) + { + Local0 = PID_GPIOCOM5 + } + + Default + { + Return (0) + } + } + Return (Local0) +} diff --git a/src/soc/intel/xeon_sp/acpi/pch.asl b/src/soc/intel/xeon_sp/acpi/pch.asl index 98a5fdd..fef68b0 100644 --- a/src/soc/intel/xeon_sp/acpi/pch.asl +++ b/src/soc/intel/xeon_sp/acpi/pch.asl @@ -2,5 +2,8 @@
/* This file should be included in the proper platform ACPI _SB PCI scope */
+/* GPIO */ +#include <soc/intel/xeon_sp/acpi/gpio.asl> + /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index f9c3644..a51b58c 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -33,5 +33,6 @@ #define PCH_PWRM_BASE_SIZE 0x10000
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define GPIO_BASE_SIZE 0x10000
#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h index 2517fb8..4d3ad7a 100644 --- a/src/soc/intel/xeon_sp/include/soc/irq.h +++ b/src/soc/intel/xeon_sp/include/soc/irq.h @@ -5,5 +5,6 @@
#define PCH_IRQ10 10 #define PCH_IRQ11 11 +#define PCH_IRQ14 14
#endif /* _SOC_IRQ_H_ */
-
Angel Pons (Code Review) -
Jingle Hsu (Code Review)
-
Johnny Lin (Code Review)
-
Jonathan Zhang (Code Review)
-
Lance Zhao (Code Review)
-
Maxim Polyakov (Code Review)
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Patrick Georgi (Code Review)