Maxim Polyakov has uploaded this change for review.
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
A src/soc/intel/xeon_sp/acpi/gpio.asl
1 file changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/1
diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl
new file mode 100644
index 0000000..4a981b7
--- /dev/null
+++ b/src/soc/intel/xeon_sp/acpi/gpio.asl
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+#include <soc/gpio.h>
+
+#define GPIOTXSTATE_MASK 0x1
+#define GPIORXSTATE_MASK 0x1
+
+Device (GPIO)
+{
+ Name (_HID, "INT3536")
+ Name (_UID, 1)
+ Name (_DDN, "GPIO Controller")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0, COM0)
+ Memory32Fixed (ReadWrite, 0, 0, COM1)
+ Memory32Fixed (ReadWrite, 0, 0, COM3)
+ Memory32Fixed (ReadWrite, 0, 0, COM4)
+ Memory32Fixed (ReadWrite, 0, 0, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { 0 }
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ /* GPIO Community 0 */
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+ Store (^^PCRB (PID_GPIOCOM0), BAS0)
+ Store (GPIO_BASE_SIZE, LEN0)
+
+ /* GPIO Community 1 */
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+ Store (^^PCRB (PID_GPIOCOM1), BAS1)
+ Store (GPIO_BASE_SIZE, LEN1)
+
+ /* GPIO Community 3 */
+ CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
+ CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
+ Store (^^PCRB (PID_GPIOCOM3), BAS3)
+ Store (GPIO_BASE_SIZE, LEN3)
+
+ /* GPIO Community 4 */
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+ Store (^^PCRB (PID_GPIOCOM4), BAS4)
+ Store (GPIO_BASE_SIZE, LEN4)
+
+ /* GPIO Community 5 */
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
+ Store (^^PCRB (PID_GPIOCOM5), BAS5)
+ Store (GPIO_BASE_SIZE, LEN5)
+
+ CreateDWordField (^RBUF, ^GIRQ._INT, IRQN)
+ And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG),
+ GPIO_DRIVER_IRQ_ROUTE_MASK, Local0)
+
+ /* TODO: Check this!
+ If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) {
+ Store (GPIO_IRQ14, IRQN)
+ } Else {
+ Store (GPIO_IRQ15, IRQN)
+ }
+ */
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+ /* GPIO Community 0 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_F23)))
+ {
+ Store (PID_GPIOCOM0, Local0)
+ Subtract (Arg0, GPP_A0, Local1)
+ }
+ /* GPIO Community 1 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23)))
+ {
+ Store (PID_GPIOCOM1, Local0)
+ Subtract (Arg0, GPP_C0, Local1)
+ }
+ /* GPIO Community 3 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10)))
+ {
+ Store (PID_GPIOCOM3, Local0)
+ Subtract (Arg0, GPP_I0, Local1)
+ }
+ /* GPIO Community 4 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_J0), LLessEqual (Arg0, GPP_K10)))
+ {
+ Store (PID_GPIOCOM4, Local0)
+ Subtract (Arg0, GPP_J0, Local1)
+ }
+ /* GPIO Community 5 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_L19)))
+ {
+ Store (PID_GPIOCOM5, Local0)
+ Subtract (Arg0, GPP_G0, Local1)
+ }
+ Store (PCRB (Local0), Local2)
+ Add (Local2, PAD_CFG_BASE, Local2)
+ Return (Add (Local2, Multiply (Local1, 8)))
+}
+
+/*
+ * Get GPIO Rx Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Get GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (GTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Set GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (STXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Or (GPIOTXSTATE_MASK, VAL0, VAL0)
+}
+
+/*
+ * Clear GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (CTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (Not (GPIOTXSTATE_MASK), VAL0, VAL0)
+}
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