Yanjie Jiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32666
Change subject: coreboot: add md power off flow ......................................................................
coreboot: add md power off flow
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/mt8183.c 4 files changed, 67 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32666/1
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc old mode 100644 new mode 100755 index 5392a9e..ca7d521 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +bootblock-y += md_ctrl.c
decompressor-y += decompressor.c decompressor-y += ../common/mmu_operations.c @@ -21,6 +22,7 @@ verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c +verstage-y += md_ctrl.c
romstage-y += auxadc.c romstage-y += ../common/cbmem.c emi.c @@ -39,6 +41,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c +romstage-y += md_ctrl.c
ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c diff --git a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h new file mode 100755 index 0000000..534de9b --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MD_POWER_H__ +#define __SOC_MEDIATEK_MD_POWER_H__ + +void mtk_md_early_init(void); + +#endif \ No newline at end of file diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c new file mode 100755 index 0000000..c8acb1f --- /dev/null +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/md_ctrl.h> + +static void internal_md1_power_down(void) +{ + unsigned int reg_value; + + /* 1. md clock setting: gating */ + reg_value = read32(&mtk_topckgen->clk_mode); + reg_value |= ((1<<8)|(1<<9)); + write32(&mtk_topckgen->clk_mode, reg_value); + + /* 2. mixedsys topsm init, for release srcclkena in kernel */ + reg_value = read32(&mt8183_infracfg->infra_misc2); + reg_value &= ~0xFF; + write32(&mt8183_infracfg->infra_misc2, reg_value); + + printk(BIOS_INFO, "[ccci-off]src clk ena = 0x%X\n", + read32(&mt8183_infracfg->infra_misc2)); +} + +void mtk_md_early_init(void) +{ + internal_md1_power_down(); +} + diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c old mode 100644 new mode 100755 index c441980..66038e3 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -15,8 +15,10 @@
#include <soc/mt8183.h> #include <soc/wdt.h> +#include <soc/md_ctrl.h>
void mt8183_early_init(void) { mtk_wdt_init(); + mtk_md_early_init(); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: coreboot: add md power off flow ......................................................................
Patch Set 1:
(63 comments)
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... File src/soc/mediatek/mt8183/include/soc/md_ctrl.h:
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 1: /* trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 2: * Copyright (C) 2019 MediaTek Inc. trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 3: * trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 4: * This program is free software: you can redistribute it and/or modify trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 5: * it under the terms of the GNU General Public License version 2 as trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 6: * published by the Free Software Foundation. trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 7: * trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 8: * This program is distributed in the hope that it will be useful, trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 9: * but WITHOUT ANY WARRANTY; without even the implied warranty of trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 11: * GNU General Public License for more details. trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 12: */ DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 13: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 14: #ifndef __SOC_MEDIATEK_MD_POWER_H__ DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 15: #define __SOC_MEDIATEK_MD_POWER_H__ DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 16: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 17: void mtk_md_early_init(void); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 18: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 19: #endif adding a line without newline at end of file
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@1 PS1, Line 1: /* trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@2 PS1, Line 2: * Copyright (C) 2019 MediaTek Inc. trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@3 PS1, Line 3: * trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@4 PS1, Line 4: * This program is free software: you can redistribute it and/or modify trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@5 PS1, Line 5: * it under the terms of the GNU General Public License version 2 as trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@6 PS1, Line 6: * published by the Free Software Foundation. trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@7 PS1, Line 7: * trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@8 PS1, Line 8: * This program is distributed in the hope that it will be useful, trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@9 PS1, Line 9: * but WITHOUT ANY WARRANTY; without even the implied warranty of trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@10 PS1, Line 10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@11 PS1, Line 11: * GNU General Public License for more details. trailing whitespace
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@12 PS1, Line 12: */ DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@13 PS1, Line 13: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@13 PS1, Line 13: please, no spaces at the start of a line
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@14 PS1, Line 14: #include <device/mmio.h> DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@15 PS1, Line 15: #include <console/console.h> DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@16 PS1, Line 16: #include <soc/addressmap.h> DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@17 PS1, Line 17: #include <soc/infracfg.h> DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@18 PS1, Line 18: #include <soc/pll.h> DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@19 PS1, Line 19: #include <soc/md_ctrl.h> DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@20 PS1, Line 20: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@21 PS1, Line 21: static void internal_md1_power_down(void) DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@22 PS1, Line 22: { DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@23 PS1, Line 23: unsigned int reg_value; DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@24 PS1, Line 24: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@25 PS1, Line 25: /* 1. md clock setting: gating */ DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@26 PS1, Line 26: reg_value = read32(&mtk_topckgen->clk_mode); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@27 PS1, Line 27: reg_value |= ((1<<8)|(1<<9)); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@28 PS1, Line 28: write32(&mtk_topckgen->clk_mode, reg_value); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@29 PS1, Line 29: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@30 PS1, Line 30: /* 2. mixedsys topsm init, for release srcclkena in kernel */ DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@31 PS1, Line 31: reg_value = read32(&mt8183_infracfg->infra_misc2); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@32 PS1, Line 32: reg_value &= ~0xFF; DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@33 PS1, Line 33: write32(&mt8183_infracfg->infra_misc2, reg_value); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@34 PS1, Line 34: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@35 PS1, Line 35: printk(BIOS_INFO, "[ccci-off]src clk ena = 0x%X\n", DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@36 PS1, Line 36: read32(&mt8183_infracfg->infra_misc2)); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@37 PS1, Line 37: } DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@38 PS1, Line 38: DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@39 PS1, Line 39: void mtk_md_early_init(void) DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@40 PS1, Line 40: { DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@41 PS1, Line 41: internal_md1_power_down(); DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@42 PS1, Line 42: } DOS line endings
https://review.coreboot.org/#/c/32666/1/src/soc/mediatek/mt8183/md_ctrl.c@43 PS1, Line 43: DOS line endings
Yanjie Jiang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: coreboot: add md power off flow ......................................................................
Patch Set 1:
This change is ready for review.
Yanjie Jiang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 6:
This change is ready for review.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 6:
(8 comments)
https://review.coreboot.org/#/c/32666/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32666/6//COMMIT_MSG@9 PS6, Line 9: make suspend fail. fail suspend/resume.
https://review.coreboot.org/#/c/32666/6//COMMIT_MSG@9 PS6, Line 9: 26M clock will be hold by srcclkena SRCCLKENA holds 26M clock
https://review.coreboot.org/#/c/32666/6//COMMIT_MSG@10 PS6, Line 10: on by
https://review.coreboot.org/#/c/32666/6//COMMIT_MSG@10 PS6, Line 10: , so we release it. so we can simply release it for suspend/resume to work.
https://review.coreboot.org/#/c/32666/6//COMMIT_MSG@10 PS6, Line 10: srcclkena SRCCLKENA
https://review.coreboot.org/#/c/32666/6/src/soc/mediatek/mt8183/md_ctrl.c File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/#/c/32666/6/src/soc/mediatek/mt8183/md_ctrl.c@23 PS6, Line 23: (1 << 8) | (1 << 9) Do these have good reg constant names?
If possible, please define them as enum (can be in the .c file), and then use the named constant here to make it more meaningful.
https://review.coreboot.org/#/c/32666/6/src/soc/mediatek/mt8183/md_ctrl.c@25 PS6, Line 25: 0xFF also make a constant for this.
https://review.coreboot.org/#/c/32666/6/src/soc/mediatek/mt8183/soc.c File src/soc/mediatek/mt8183/soc.c:
https://review.coreboot.org/#/c/32666/6/src/soc/mediatek/mt8183/soc.c@20 PS6, Line 20: #include <soc/md_ctrl.h> order header files (i.e., move to before mmu_operations.h
Hello Julius Werner, Tristan Hsieh, build bot (Jenkins), Weiyi Lu, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32666
to look at the new patch set (#7).
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
mediatek/mt8183: Add md power off flow
SRCCLKENA holds 26M clock, and it will fail suspend/resume. The SRCCLKENA is not used by mt8183, so we can simply release it for suspend/resume to work.
BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui, suspend test.
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Signed-off-by: Yanjie.jiang yanjie.jiang@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/soc.c 4 files changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32666/7
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
just some nits.
@jwerner I think this seems ok. Time to take a final review?
https://review.coreboot.org/#/c/32666/7/src/soc/mediatek/mt8183/md_ctrl.c File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/#/c/32666/7/src/soc/mediatek/mt8183/md_ctrl.c@28 PS7, Line 28: ( no need to quote since this is one single arg.
TOPCKGEN_CLK ... | TOPCKGEN...);
Hello Julius Werner, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Weiyi Lu, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32666
to look at the new patch set (#8).
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
mediatek/mt8183: Add md power off flow
SRCCLKENA holds 26M clock, and it will fail suspend/resume. The SRCCLKENA is not used by mt8183, so we can simply release it for suspend/resume to work.
BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui, suspend test.
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Signed-off-by: Yanjie.jiang yanjie.jiang@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/soc.c 4 files changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32666/8
You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 8: Code-Review+1
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 8: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 8:
(6 comments)
https://review.coreboot.org/#/c/32666/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32666/8//COMMIT_MSG@7 PS8, Line 7: power off power-off
https://review.coreboot.org/#/c/32666/8//COMMIT_MSG@10 PS8, Line 10: The SRCCLKENA is not used by mt8183, : so we can simply release it for suspend/resume to work. Please do not break the, just because there is a comma.
https://review.coreboot.org/#/c/32666/8//COMMIT_MSG@15 PS8, Line 15: Test=Boots correctly on Kukui, suspend test. Before it did not suspend or resume correctly?
https://review.coreboot.org/#/c/32666/8/src/soc/mediatek/mt8183/md_ctrl.c File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/#/c/32666/8/src/soc/mediatek/mt8183/md_ctrl.c@26 PS8, Line 26: /* Gating MD clock. */ Remove the dot at the end?
https://review.coreboot.org/#/c/32666/8/src/soc/mediatek/mt8183/md_ctrl.c@29 PS8, Line 29: /* Release SRCCLKENA. */ Ditto.
https://review.coreboot.org/#/c/32666/8/src/soc/mediatek/mt8183/md_ctrl.c@31 PS8, Line 31: INFRA_MISC2_SRCCLKENA_RELEASE); Doesn’t that fit on one line?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 8: Code-Review+1
Please revise according to Paul's comments before we can move on.
Yanjie Jiang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... PS8, Line 31: INFRA_MISC2_SRCCLKENA_RELEASE);
Doesn’t that fit on one line?
clrbits_le32(&mt8183_infracfg->infra_misc2, INFRA_MISC2_SRCCLKENA_RELEASE); will > 80 characters, to 84 characters.
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Weiyi Lu, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32666
to look at the new patch set (#9).
Change subject: mediatek/mt8183: Add md power off flow ......................................................................
mediatek/mt8183: Add md power off flow
SRCCLKENA holds 26M clock, which will fail suspend/resume, and the SRCCLKENA is not used by mt8183, so we can simply release it for suspend/resume to work.
BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui, suspend test pass.
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Signed-off-by: Yanjie.jiang yanjie.jiang@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/soc.c 4 files changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32666/9
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Weiyi Lu, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32666
to look at the new patch set (#10).
Change subject: mediatek/mt8183: Add md power-off flow ......................................................................
mediatek/mt8183: Add md power-off flow
SRCCLKENA holds 26M clock, which will fail suspend/resume, and the SRCCLKENA is not used by mt8183, so we can simply release it for suspend/resume to work.
BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui, suspend test pass.
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Signed-off-by: Yanjie.jiang yanjie.jiang@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/soc.c 4 files changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32666/10
Yanjie Jiang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power-off flow ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/32666/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/32666/8//COMMIT_MSG@15 PS8, Line 15: Test=Boots correctly on Kukui, suspend test.
Before it did not suspend or resume correctly?
Yes, will fail suspend/resume.
https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... PS8, Line 26: /* Gating MD clock. */
Remove the dot at the end?
deleted
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power-off flow ......................................................................
Patch Set 10: Code-Review+2
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power-off flow ......................................................................
Patch Set 10:
Could you mark all of the comments that have been addressed as "Done" or "Ack"?
Thanks.
Yanjie Jiang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power-off flow ......................................................................
Patch Set 10:
(87 comments)
https://review.coreboot.org/c/coreboot/+/32666/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/32666/1//COMMIT_MSG@2 PS1, Line 2: yanjie.jiang
Please spell it Yanjie Jiang. […]
Done
https://review.coreboot.org/c/coreboot/+/32666/1//COMMIT_MSG@8 PS1, Line 8:
Why prefix with coreboot? Please look at `git log --oneline` how to format the summaries. […]
Done
https://review.coreboot.org/c/coreboot/+/32666/1//COMMIT_MSG@10 PS1, Line 10:
Signed-off-by line is missing.
Done
https://review.coreboot.org/c/coreboot/+/32666/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/32666/5//COMMIT_MSG@10 PS5, Line 10: no
not
Done
https://review.coreboot.org/c/coreboot/+/32666/5//COMMIT_MSG@17 PS5, Line 17: yanjie.jiang
Please update this string too.
Done
https://review.coreboot.org/c/coreboot/+/32666/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/32666/6//COMMIT_MSG@9 PS6, Line 9: 26M clock will be hold by srcclkena
SRCCLKENA holds 26M clock
Done
https://review.coreboot.org/c/coreboot/+/32666/6//COMMIT_MSG@9 PS6, Line 9: make suspend fail.
fail suspend/resume.
Done
https://review.coreboot.org/c/coreboot/+/32666/6//COMMIT_MSG@10 PS6, Line 10: , so we release it.
so we can simply release it for suspend/resume to work.
Done
https://review.coreboot.org/c/coreboot/+/32666/6//COMMIT_MSG@10 PS6, Line 10: srcclkena
SRCCLKENA
Done
https://review.coreboot.org/c/coreboot/+/32666/6//COMMIT_MSG@10 PS6, Line 10: on
by
Done
https://review.coreboot.org/c/coreboot/+/32666/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/32666/8//COMMIT_MSG@7 PS8, Line 7: power off
power-off
Done
https://review.coreboot.org/c/coreboot/+/32666/8//COMMIT_MSG@10 PS8, Line 10: The SRCCLKENA is not used by mt8183, : so we can simply release it for suspend/resume to work.
Please do not break the, just because there is a comma.
Done
https://review.coreboot.org/c/coreboot/+/32666/8//COMMIT_MSG@15 PS8, Line 15: Test=Boots correctly on Kukui, suspend test.
Yes, will fail suspend/resume.
Done
https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/md_ctrl.h:
https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 1: /*
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 2: * Copyright (C) 2019 MediaTek Inc.
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 4: * This program is free software: you can redistribute it and/or modify
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 9: * but WITHOUT ANY WARRANTY; without even the implied warranty of
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 12: */
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 13:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 14: #ifndef __SOC_MEDIATEK_MD_POWER_H__
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 15: #define __SOC_MEDIATEK_MD_POWER_H__
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 16:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 17: void mtk_md_early_init(void);
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/inc... PS1, Line 19: #endif
adding a line without newline at end of file
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 1: /*
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 2: * Copyright (C) 2019 MediaTek Inc.
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 5: * it under the terms of the GNU General Public License version 2 as
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 6: * published by the Free Software Foundation.
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 12: */
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 13:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 13:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 14: #include <device/mmio.h>
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 15: #include <console/console.h>
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 16: #include <soc/addressmap.h>
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 17: #include <soc/infracfg.h>
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 18: #include <soc/pll.h>
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 19: #include <soc/md_ctrl.h>
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 20:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 21: static void internal_md1_power_down(void)
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 22: {
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 23: unsigned int reg_value;
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 24:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 25: /* 1. md clock setting: gating */
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 26: reg_value = read32(&mtk_topckgen->clk_mode);
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 27: reg_value |= ((1<<8)|(1<<9));
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 28: write32(&mtk_topckgen->clk_mode, reg_value);
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 29:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 30: /* 2. mixedsys topsm init, for release srcclkena in kernel */
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 31: reg_value = read32(&mt8183_infracfg->infra_misc2);
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 32: reg_value &= ~0xFF;
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 33: write32(&mt8183_infracfg->infra_misc2, reg_value);
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 34:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 35: printk(BIOS_INFO, "[ccci-off]src clk ena = 0x%X\n",
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 36: read32(&mt8183_infracfg->infra_misc2));
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 37: }
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 38:
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 39: void mtk_md_early_init(void)
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 40: {
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 41: internal_md1_power_down();
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 42: }
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https://review.coreboot.org/c/coreboot/+/32666/1/src/soc/mediatek/mt8183/md_... PS1, Line 43:
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https://review.coreboot.org/c/coreboot/+/32666/2/src/soc/mediatek/mt8183/md_... File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/c/coreboot/+/32666/2/src/soc/mediatek/mt8183/md_... PS2, Line 13:
please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/32666/2/src/soc/mediatek/mt8183/md_... PS2, Line 13:
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https://review.coreboot.org/c/coreboot/+/32666/2/src/soc/mediatek/mt8183/md_... PS2, Line 23: setbits_le32(&mtk_topckgen->clk_mode, ((1<<8)|(1<<9)));
code indent should use tabs where possible
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https://review.coreboot.org/c/coreboot/+/32666/2/src/soc/mediatek/mt8183/md_... PS2, Line 23: setbits_le32(&mtk_topckgen->clk_mode, ((1<<8)|(1<<9)));
please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/32666/6/src/soc/mediatek/mt8183/md_... File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/c/coreboot/+/32666/6/src/soc/mediatek/mt8183/md_... PS6, Line 23: (1 << 8) | (1 << 9)
Do these have good reg constant names? […]
Done
https://review.coreboot.org/c/coreboot/+/32666/6/src/soc/mediatek/mt8183/md_... PS6, Line 25: 0xFF
also make a constant for this.
Done
https://review.coreboot.org/c/coreboot/+/32666/7/src/soc/mediatek/mt8183/md_... File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/c/coreboot/+/32666/7/src/soc/mediatek/mt8183/md_... PS7, Line 28: (
no need to quote since this is one single arg. […]
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https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... File src/soc/mediatek/mt8183/md_ctrl.c:
https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... PS8, Line 26: /* Gating MD clock. */
deleted
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https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... PS8, Line 29: /* Release SRCCLKENA. */
Ditto.
Done
https://review.coreboot.org/c/coreboot/+/32666/8/src/soc/mediatek/mt8183/md_... PS8, Line 31: INFRA_MISC2_SRCCLKENA_RELEASE);
clrbits_le32(&mt8183_infracfg->infra_misc2, INFRA_MISC2_SRCCLKENA_RELEASE); […]
Ack
https://review.coreboot.org/c/coreboot/+/32666/6/src/soc/mediatek/mt8183/soc... File src/soc/mediatek/mt8183/soc.c:
https://review.coreboot.org/c/coreboot/+/32666/6/src/soc/mediatek/mt8183/soc... PS6, Line 20: #include <soc/md_ctrl.h>
order header files (i.e., move to before mmu_operations. […]
Done
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32666 )
Change subject: mediatek/mt8183: Add md power-off flow ......................................................................
mediatek/mt8183: Add md power-off flow
SRCCLKENA holds 26M clock, which will fail suspend/resume, and the SRCCLKENA is not used by mt8183, so we can simply release it for suspend/resume to work.
BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui, suspend test pass.
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Signed-off-by: Yanjie.jiang yanjie.jiang@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32666 Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/md_ctrl.h A src/soc/mediatek/mt8183/md_ctrl.c M src/soc/mediatek/mt8183/soc.c 4 files changed, 59 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 0a79ed7..edf71a8 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += md_ctrl.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h new file mode 100644 index 0000000..059bf9b --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MD_CTRL_H__ +#define __SOC_MEDIATEK_MD_CTRL_H__ + +void mtk_md_early_init(void); + +#endif diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c new file mode 100644 index 0000000..aa97756 --- /dev/null +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/md_ctrl.h> + +#define TOPCKGEN_CLK_MODE_MD_32K (1 << 8) +#define TOPCKGEN_CLK_MODE_MD_26M (1 << 9) +#define INFRA_MISC2_SRCCLKENA_RELEASE (0xFF) + +static void internal_md_power_down(void) +{ + /* Gating MD clock */ + setbits_le32(&mtk_topckgen->clk_mode, + TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M); + /* Release SRCCLKENA */ + clrbits_le32(&mt8183_infracfg->infra_misc2, + INFRA_MISC2_SRCCLKENA_RELEASE); +} + +void mtk_md_early_init(void) +{ + internal_md_power_down(); +} diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index b51e7d4..501ae19 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -15,10 +15,10 @@
#include <device/device.h> #include <soc/emi.h> +#include <soc/md_ctrl.h> #include <soc/mmu_operations.h> #include <symbols.h>
- static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); @@ -27,6 +27,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + mtk_md_early_init(); }
static struct device_operations soc_ops = {
-
build bot (Jenkins) (Code Review) -
Hung-Te Lin (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Yanjie Jiang (Code Review)
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You-Cheng Syu (Code Review)