63 comments:
File src/soc/mediatek/mt8183/include/soc/md_ctrl.h:
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Patch Set #1, Line 2: * Copyright (C) 2019 MediaTek Inc.
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Patch Set #1, Line 4: * This program is free software: you can redistribute it and/or modify
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Patch Set #1, Line 5: * it under the terms of the GNU General Public License version 2 as
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Patch Set #1, Line 6: * published by the Free Software Foundation.
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Patch Set #1, Line 8: * This program is distributed in the hope that it will be useful,
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Patch Set #1, Line 9: * but WITHOUT ANY WARRANTY; without even the implied warranty of
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Patch Set #1, Line 10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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Patch Set #1, Line 11: * GNU General Public License for more details.
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Patch Set #1, Line 14: #ifndef __SOC_MEDIATEK_MD_POWER_H__
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Patch Set #1, Line 15: #define __SOC_MEDIATEK_MD_POWER_H__
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Patch Set #1, Line 17: void mtk_md_early_init(void);
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Patch Set #1, Line 19: #endif
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File src/soc/mediatek/mt8183/md_ctrl.c:
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Patch Set #1, Line 2: * Copyright (C) 2019 MediaTek Inc.
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Patch Set #1, Line 4: * This program is free software: you can redistribute it and/or modify
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Patch Set #1, Line 5: * it under the terms of the GNU General Public License version 2 as
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Patch Set #1, Line 6: * published by the Free Software Foundation.
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Patch Set #1, Line 8: * This program is distributed in the hope that it will be useful,
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Patch Set #1, Line 9: * but WITHOUT ANY WARRANTY; without even the implied warranty of
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Patch Set #1, Line 10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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Patch Set #1, Line 11: * GNU General Public License for more details.
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Patch Set #1, Line 14: #include <device/mmio.h>
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Patch Set #1, Line 15: #include <console/console.h>
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Patch Set #1, Line 16: #include <soc/addressmap.h>
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Patch Set #1, Line 17: #include <soc/infracfg.h>
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Patch Set #1, Line 18: #include <soc/pll.h>
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Patch Set #1, Line 19: #include <soc/md_ctrl.h>
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Patch Set #1, Line 21: static void internal_md1_power_down(void)
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Patch Set #1, Line 23: unsigned int reg_value;
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Patch Set #1, Line 25: /* 1. md clock setting: gating */
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Patch Set #1, Line 26: reg_value = read32(&mtk_topckgen->clk_mode);
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Patch Set #1, Line 27: reg_value |= ((1<<8)|(1<<9));
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Patch Set #1, Line 28: write32(&mtk_topckgen->clk_mode, reg_value);
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Patch Set #1, Line 30: /* 2. mixedsys topsm init, for release srcclkena in kernel */
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Patch Set #1, Line 31: reg_value = read32(&mt8183_infracfg->infra_misc2);
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Patch Set #1, Line 32: reg_value &= ~0xFF;
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Patch Set #1, Line 33: write32(&mt8183_infracfg->infra_misc2, reg_value);
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Patch Set #1, Line 35: printk(BIOS_INFO, "[ccci-off]src clk ena = 0x%X\n",
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Patch Set #1, Line 36: read32(&mt8183_infracfg->infra_misc2));
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Patch Set #1, Line 39: void mtk_md_early_init(void)
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Patch Set #1, Line 41: internal_md1_power_down();
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