Change in coreboot[master]: drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

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Arthur Heymans (Code Review)

14 Oct 2020 14 Oct '20

10 a.m.

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Since we change the caching setup it is probably a good idea to make sure our saved MTRR setup hits dram.

Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46376/1

diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 563dc08..31f41ed 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -107,6 +107,7 @@ movl %cr0, %eax orl $(CR0_CD | CR0_NW), %eax movl %eax, %cr0 + wbinvd

/* Disable fixed MTRRs */ movl $(MTRR_DEF_TYPE_MSR), %ecx

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Angel Pons (Code Review)

14 Oct 14 Oct

10:29 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 1: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 08:29:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Christian Walter (Code Review)

10:43 a.m.

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 1: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 08:43:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

11:29 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: drivers/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46376/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/46376/1//COMMIT_MSG@7 PS1, Line 7: drivers nit: security/intel or sec/intel

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 09:29:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Arthur Heymans (Code Review)

12:09 p.m.

New subject: Change in coreboot[master]: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Hello build bot (Jenkins), Christian Walter, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46376

to look at the new patch set (#2).

Change subject: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Since we change the caching setup it is probably a good idea to make sure our saved MTRR setup hits dram.

Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46376/2

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Angel Pons (Code Review)

12:26 p.m.

New subject: Change in coreboot[master]: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 2: Code-Review+2

Tested on Haswell, BIOS ACM is still happy about things.

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 10:26:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Philipp Deppenwiese (Code Review)

1:43 p.m.

New subject: Change in coreboot[master]: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 2: Code-Review-1

Dies on Deletalake hardware as soon as getsec lockdown is called

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 11:43:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

1:53 p.m.

New subject: Change in coreboot[master]: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 2: -Code-Review

...

Patch Set 2: Code-Review-1

Dies on Deletalake hardware as soon as getsec lockdown is called

Ah, good point. Haswell doesn't have lockdown.

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 11:53:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Arthur Heymans (Code Review)

1:56 p.m.

New subject: Change in coreboot[master]: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 2: Code-Review-2

...

Patch Set 2: Code-Review-1

Dies on Deletalake hardware as soon as getsec lockdown is called

Looks like lockdown specifically needs wbinvd to be skipped...

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 11:56:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Arthur Heymans (Code Review)

2:49 p.m.

New subject: Change in coreboot[master]: [TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits ...

Hello Philipp Deppenwiese, build bot (Jenkins), Christian Walter, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46376

to look at the new patch set (#3).

Change subject: [TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

[TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Since we change the caching setup it is probably a good idea to make sure our saved MTRR setup hits dram.

Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46376/3

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Angel Pons (Code Review)

3:21 p.m.

New subject: Change in coreboot[master]: [TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits ...

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: [TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46376/3/src/security/intel/txt/gets... File src/security/intel/txt/getsec_enteraccs.S:

https://review.coreboot.org/c/coreboot/+/46376/3/src/security/intel/txt/gets... PS3, Line 111: Writeback nit: `Write back`, and also comment style

https://review.coreboot.org/c/coreboot/+/46376/3/src/security/intel/txt/gets... PS3, Line 114: SCLEAN On Haswell, I need a slightly different prologue for SCLEAN in romstage. The MTRR algorithm is pretty much the same, though

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 14 Oct 2020 13:21:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Arthur Heymans (Code Review)

21 Apr 21 Apr

2:01 p.m.

New subject: Change in coreboot[master]: [TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits ...

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46376 )

Change subject: [TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram ......................................................................

Abandoned

Not needed anymore.

-- To view, visit https://review.coreboot.org/c/coreboot/+/46376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330 Gerrit-Change-Number: 46376 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Christian Walter christian.walter@9elements.com Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-MessageType: abandon

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Angel Pons (Code Review)
Arthur Heymans (Code Review)
Christian Walter (Code Review)
Philipp Deppenwiese (Code Review)