Arthur Heymans uploaded patch set #3 to this change.

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[TEST]sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Since we change the caching setup it is probably a good idea to make
sure our saved MTRR setup hits dram.

Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330
Signed-off-by: Arthur Heymans <>
M src/security/intel/txt/getsec_enteraccs.S
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh:// refs/changes/76/46376/3

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330
Gerrit-Change-Number: 46376
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <>
Gerrit-Reviewer: Angel Pons <>
Gerrit-Reviewer: Arthur Heymans <>
Gerrit-Reviewer: Christian Walter <>
Gerrit-Reviewer: Philipp Deppenwiese <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-MessageType: newpatchset