Arthur Heymans uploaded patch set #2 to this change.

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sec/intel/txt/getsec_enteraccs.S: Make sure the MTRR save hits dram

Since we change the caching setup it is probably a good idea to make
sure our saved MTRR setup hits dram.

Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/security/intel/txt/getsec_enteraccs.S
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46376/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifa04f6de8af35c043fe049bc9a1bd3a8a4f1c330
Gerrit-Change-Number: 46376
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Christian Walter <christian.walter@9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset