Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33740
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explaing LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md 5 files changed, 272 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/1
diff --git a/Documentation/soc/intel/apollolake/flash_layout.dia b/Documentation/soc/intel/apollolake/flash_layout.dia index 4ea5440..a329620 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.dia +++ b/Documentation/soc/intel/apollolake/flash_layout.dia Binary files differ diff --git a/Documentation/soc/intel/apollolake/flash_layout.svg b/Documentation/soc/intel/apollolake/flash_layout.svg index 9322875..07b3a58 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.svg +++ b/Documentation/soc/intel/apollolake/flash_layout.svg @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> -<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> +<svg width="38cm" height="19cm" viewBox="118 61 744 380" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> <g> <rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/> <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/> @@ -16,18 +16,18 @@ <tspan x="460" y="134.425">BIOS</tspan> </text> <g> - <rect style="fill: #ffffff" x="240" y="100" width="60" height="60"/> - <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="240" y="100" width="60" height="60"/> + <rect style="fill: #ffffff" x="227.633" y="99.4585" width="60" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="227.633" y="99.4585" width="60" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="270" y="134.425"> - <tspan x="270" y="134.425">IFD</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="257.633" y="133.884"> + <tspan x="257.633" y="133.884">IFD</tspan> </text> <g> <rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/> <rect style="fill: none; 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fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 120 380 C 120,320 240,360 240,311"/> + <polygon style="fill: #000000" points="245,311 240,301 235,311 "/> + <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/> + </g> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="247.944" y="231.664"> + <tspan x="247.944" y="231.664">Logical Boot Partition 1</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="644.3" y="90.55"> + <tspan x="644.3" y="90.55">TXE private partition</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="768" y="77.25"> + <tspan x="768" y="77.25"></tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="739" y="77.25"> + <tspan x="739" y="77.25"></tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="389.3" y="90.55"> + <tspan x="389.3" y="90.55">TXE / BIOS shared partition</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="288.32" y="99.2492" width="11.6609" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="288.32" y="99.2492" width="11.6609" height="60"/> + </g> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="232.974" y="73.4916"> + <tspan x="232.974" y="73.4916">ME region (unused)</tspan> + </text> + <g> + <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x1="295.224" y1="77.2138" x2="295.23" y2="86.6145"/> + <polygon style="fill: #000000" points="295.235,94.1145 290.228,84.1177 295.23,86.6145 300.228,84.1114 "/> + <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="295.235,94.1145 290.228,84.1177 295.23,86.6145 300.228,84.1114 "/> + </g> + <g> + <rect style="fill: #ffffff" x="511.814" y="240" width="188.474" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="511.814" y="240" width="188.474" height="60"/> + </g> + <g> + <rect style="fill: #ffffff" x="440.696" y="240.49" width="71.1194" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="440.696" y="240.49" width="71.1194" height="60"/> + </g> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="606.052" y="274.425"> + <tspan x="606.052" y="274.425">OBB</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="476.254" y="274.915"> + <tspan x="476.254" y="274.915">IFWI</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="493.642" y="231.092"> + <tspan x="493.642" y="231.092">Logical Boot Partition 2</tspan> + </text> + <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke-dasharray: 4; stroke: #000000" x1="439.69" y1="207.594" x2="440.696" y2="240.49"/> + <g> + <rect style="fill: #d8e5e5" x="668.7" y="241.9" width="28.5491" height="54.6579"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="668.7" y="241.9" width="28.5491" height="54.6579"/> + </g> +</svg> diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md index d4a5ee5..3ff0027 100644 --- a/Documentation/soc/intel/apollolake/index.md +++ b/Documentation/soc/intel/apollolake/index.md @@ -1,9 +1,7 @@ # Apollolake -## SPI flash layout
-![][apl_flash_layout] - -With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image). +With Apollolake Intel invented another flash layout for x86 firmware called +IFWI (Intel FirmWare Image).
Usually on x86 platforms the bootblock is stored at the end of the bios region and the Intel ME / TXE has its own IFD region. On Apollolake both have been @@ -12,6 +10,47 @@
The IFWI region can be manipulated by `ifwitool`.
-[apl_flash_layout]: flash_layout.svg +## SPI flash layout
+IFD regions: +* The "ME" region isn't used on production boards +* The "BIOS" region contains one or two logical boot partitions (LBP) + * The IFD controls if one or two LBP are active + * Each LBP has it's own IFWI and OBB + * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE +* The "device extension" region is used by TXE as secure filesystem + +### SPI layout with single LBP + +When configured for single LBP mode, the LBP uses the whole "BIOS" region's +flash size. + +![][apl_flash_layout] + +### SPI layout with dual LBP + +When configured for dual LBP mode, each LBP uses exactly half of the "BIOS" +region's flash size. + +![][apl_flash_layout2] + +### IFWI + +The IFWI contains the bootblock, while the OBB contains the CBFS and other +regions as specified in the FMAP. +The OBB spans the whole size from IFWI till the end of the LBP. + +**Note:** ifwitool doesn't care about LBP2! + +### Logical boot partitions + +Each LBP has their own IFWI and OBB. It allows failsafe firmware updates. + +**Note:** If configured in dual partition mode, the TXE will enter recovery +mode if LBP2 is missing. + +To disable dual partitioning mode, set bit3 in IFD at offset `0x1ff` to 1. + +[apl_flash_layout]: flash_layout.svg +[apl_flash_layout2]: flash_layout2.svg
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/33740/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33740/1//COMMIT_MSG@9 PS1, Line 9: Explaing Explain
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 3: Apollolake Apollo Lake?
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 19: it's its
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 1:
(9 comments)
My personal agenda is as usual: Enhance flashrom to support a reasonable installation procedure. Then establish that pro- cedure in coreboot's build system and document it ;) But, as usual, this is stalled by the lack of flashrom review resources.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 4: Intel Integrated
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 8: which is a subregion of "BIOS" AFAIK, it covers the whole BIOS region.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 11: The IFWI region can be manipulated by `ifwitool`. But I wouldn't recommend it. It doesn't check if you overflow surrounding partitions when you edit a sub-partition, for instance.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 19: * Each LBP has it's own IFWI and OBB AIUI, IFWI is the whole thing, LBPs are part of the IFWI, and OBB is part of the LBP (the OBB in LBP1 is optional, in the dual LBP case).
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 20: * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE Only if you consider memory-mapping. You can still access the full region via the SPI controller. Let's say
* The BIOS region is memory-mapped at the top of 4GiB. However, the end is overlaid by an SRAM mapping. So the last 256KiB should be marked BIOS_UNUSABLE in the FMAP.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 22: Let's add here another pitfall:
* In case of 2 LBPs, the IFWI space is divided in half but each LBP should still be erase block aligned. With the usual erase block size of 4KiB, this makes the IFWI size a multiple of 8KiB. Many IFD layouts leave the last 4KiB empty to compensate for this.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 39: while the OBB contains It's part of IFWI, see above.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 47: Each LBP has their own IFWI and OBB. It allows failsafe firmware updates. Each LBP contains a Boot Partition Descriptor Table (BPDT) and a Secondary BPDT (S-BPDT). Only the BPDT partitions (boot critical) are mirrored in both LBPs, afaik.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 50: mode if LBP2 is missing. LBP2 is also supposed to contain the effective OBB in this case. But it doesn't matter with coreboot because it follows the FMAP anyway.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 1:
(1 comment)
Patch Set 1:
(9 comments)
My personal agenda is as usual: Enhance flashrom to support a reasonable installation procedure. Then establish that pro- cedure in coreboot's build system and document it ;) But, as usual, this is stalled by the lack of flashrom review resources.
I agree.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 3: Apollolake
Apollo Lake?
And please add a comma after it.
Felix Singer has uploaded a new patch set (#2) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explaing LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md 5 files changed, 274 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/2
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 3: Apollolake
And please add a comma after it.
Done
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 4: Intel
Integrated
Done
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 19: it's
its
Done
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 11: The IFWI region can be manipulated by `ifwitool`.
But I wouldn't recommend it. It doesn't check if you overflow […]
Do we want to remove this note then?
Felix Singer has uploaded a new patch set (#3) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 6 files changed, 322 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/3
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
PS3: To me, this reads totally confusing now. Wouldn't it be worth to stick to the terms Intel uses? I fear, for anyone who has more Intel than FMAP background, this document is a bummer.
Intel terms:
* IFD entries => "regions" * LBP1/LBP2 => "partitions" * upatch1/IBBP/OBBP/etc. => "sub-partitions" * sub-partitions can be "directories" => e.g. IBBP directory contains IBBL, IBB for instance
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 17: IFWI firmware components What makes them IFWI firmware components? Aren't they simply `firmware compontents`?
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 17: * Each LBP has its own copy of IFWI firmware components and OBB Why mention OBB separately? I know most FMD files treat it like that, but that's very confusing alone and not necessary. Would it be better to mention once in a prominent place that IFWI and FMD naming may differ?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/33740/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33740/2//COMMIT_MSG@9 PS2, Line 9: Explaing Explain
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 70: One blank line is enough?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 3:
This is my `default.fmd`:
FLASH 16M { SI_DESC@0 0x1000 IFWI@0x1000 0xefe000 { LBP1@0 0x77f000 { IFWI_CORE@0 0x2ff000 } LBP2@0x77f000 0x77f000 { CB_OBB@0x80000 0x200000 { # <-- @0x800000 absolute FMAP@0 0x1000 RW_MRC_CACHE@0x10000 0x10000 COREBOOT(CBFS)@0x100000 0x100000 } NOT_MEMORY_MAPPED@0x73f000 0x40000 } } DEVICE_EXPANSION@0xeff000 0x100000 UNUSED_HOLE@0xfff000 0x1000 }
"IFWI_CORE" can be used as CONFIG_IFWI_FMAP_NAME. And "CB_OBB", well, I would name it COREBOOT, but that name is already taken for CBFS :-/
I didn't push it yet, because I'm still stuck on the flashrom side. But this works fine with the current coreboot build process while it doesn't need the weirdness described in this document (i.e. redefining terms like what IFWI covers). Any name that can also be found in Intel documents should match what it says there.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 3:
(4 comments)
Please resolve all comments.
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 23: For legacy and compatibility reasons, the BIOS partition wasn't renamed to "IFWI". rephrase. It's hard to understand.
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 25: which has to be at the beginning of the BIOS region to be compliant with the seems to refer to FMAP, but doesn't say so.
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 36: To disable dual partitioning mode, set bit3 in IFD at offset `0x1ff` to 1. 0x11f
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 57: **Including components:** Included
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 58: * Intel TXE : * Power Management Controller (PMC) and P-Unit Those two are firmware as well
Felix Singer has uploaded a new patch set (#4) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 6 files changed, 322 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/4
Felix Singer has uploaded a new patch set (#5) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 6 files changed, 321 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/5
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 5:
(7 comments)
https://review.coreboot.org/c/coreboot/+/33740/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33740/1//COMMIT_MSG@9 PS1, Line 9: Explaing
Explain
Done
https://review.coreboot.org/c/coreboot/+/33740/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33740/2//COMMIT_MSG@9 PS2, Line 9: Explaing
Explain
Done
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 11: The IFWI region can be manipulated by `ifwitool`.
Do we want to remove this note then?
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 17: IFWI firmware components
What makes them IFWI firmware components? Aren't they simply `firmware compontents`?
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 36: To disable dual partitioning mode, set bit3 in IFD at offset `0x1ff` to 1.
0x11f
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 57: **Including components:**
Included
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 70:
One blank line is enough?
Done
Felix Singer has uploaded a new patch set (#6) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg A Documentation/soc/intel/apollolake/ifwi.dia A Documentation/soc/intel/apollolake/ifwi.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 8 files changed, 1,106 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/6
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 8: which is a subregion of "BIOS"
AFAIK, it covers the whole BIOS region.
Done
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 39: while the OBB contains
It's part of IFWI, see above.
Done
Felix Singer has uploaded a new patch set (#7) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg A Documentation/soc/intel/apollolake/ifwi.dia A Documentation/soc/intel/apollolake/ifwi.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 8 files changed, 1,260 insertions(+), 131 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/7
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 7: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 7:
(9 comments)
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
PS3:
To me, this reads totally confusing now. Wouldn't it be worth to stick […]
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 17: * Each LBP has its own copy of IFWI firmware components and OBB
Why mention OBB separately? I know most FMD files treat it like that, […]
Done
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 6: bios BIOS
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 19: extension expansion
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 35: \ / ?
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 44: (bootblock) They are all called bootblock somehow. Are you referring to the coreboot bootblock here? wouldn't that be the IBBL?
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 45: sub-partitions as specified in the FMAP. maybe add something like "Those are unknown to the IFWI structure." to make it clear that these are not LBP sub-partitions.
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 47: from IFWI OBB is part of an LBP, which is part of the IFWI. It doesn't start after the IFWI. Maybe just:
The OBB is always the last sub-partition of an LBP and spans to the end of the latter.
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 52: Instead we call the partition with the firmware components as "IFWI", : which has to be at the beginning of the BIOS region to be compliant with the : IFWI specification. "we" being who exactly? There is no consent in the coreboot community that I know about.
I would write:
Many custom FMAPs refer to the IFWI as all components of an LBP excluding the OBB.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/ifwi.dia:
PS7: I haven't ever seen a BPDT that points behind the S-BPDT sub partitions. Have you?
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 47: from IFWI
OBB is part of an LBP, which is part of the IFWI. It doesn't start after […]
Looking at an IFWI, it would be rather "usually spans". It seems there can be empty space after it.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/flash_layout2.svg:
PS7: Usage of IFWI is misleading here. IFWI includes both LBPs.
Felix Singer has uploaded a new patch set (#8) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg A Documentation/soc/intel/apollolake/ifwi.dia A Documentation/soc/intel/apollolake/ifwi.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 8 files changed, 1,313 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/8
Felix Singer has uploaded a new patch set (#9) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg A Documentation/soc/intel/apollolake/ifwi.dia A Documentation/soc/intel/apollolake/ifwi.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 8 files changed, 1,212 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/9
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 6: bios
BIOS
Done
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 19: extension
expansion
Done
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 35: \
/ ?
Done
Felix Singer has uploaded a new patch set (#10) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg A Documentation/soc/intel/apollolake/ifwi.dia A Documentation/soc/intel/apollolake/ifwi.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 8 files changed, 1,209 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/10
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 20: * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE
Only if you consider memory-mapping. You can still access the full […]
Done
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 22:
Let's add here another pitfall: […]
Done
Felix Singer has uploaded a new patch set (#11) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg A Documentation/soc/intel/apollolake/ifwi.dia A Documentation/soc/intel/apollolake/ifwi.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 8 files changed, 1,213 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/11
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 10:
(4 comments)
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/flash_layout2.svg:
PS7:
Usage of IFWI is misleading here. IFWI includes both LBPs.
Done
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 44: (bootblock)
They are all called bootblock somehow. Are you referring to the […]
Done
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 47: from IFWI
Looking at an IFWI, it would be rather "usually spans". It seems there […]
Done
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... PS7, Line 52: Instead we call the partition with the firmware components as "IFWI", : which has to be at the beginning of the BIOS region to be compliant with the : IFWI specification.
"we" being who exactly? There is no consent in the coreboot community that […]
Done
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 11:
(4 comments)
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 19: * Each LBP has it's own IFWI and OBB
AIUI, IFWI is the whole thing, LBPs are part of the IFWI, and OBB is part of […]
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 23: For legacy and compatibility reasons, the BIOS partition wasn't renamed to "IFWI".
rephrase. It's hard to understand.
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 25: which has to be at the beginning of the BIOS region to be compliant with the
seems to refer to FMAP, but doesn't say so.
Done
https://review.coreboot.org/c/coreboot/+/33740/3/Documentation/soc/intel/apo... PS3, Line 58: * Intel TXE : * Power Management Controller (PMC) and P-Unit
Those two are firmware as well
Done
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 11: Code-Review+1
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/ifwi.dia:
PS7:
I haven't ever seen a BPDT that points behind the S-BPDT sub partitions. […]
Well, it's explained here (p. 11) https://firmware.intel.com/sites/default/files/uefi_firmware_enabling_guide_...
Felix Singer has uploaded a new patch set (#12) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Documentation: Update soc/intel/apollolake
Explain LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Felix Singer felix.singer@9elements.com --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg A Documentation/soc/intel/apollolake/ifwi.dia A Documentation/soc/intel/apollolake/ifwi.svg M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/index.md 8 files changed, 1,216 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/12
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 47: Each LBP has their own IFWI and OBB. It allows failsafe firmware updates.
Each LBP contains a Boot Partition Descriptor Table (BPDT) and a Secondary […]
Done
https://review.coreboot.org/c/coreboot/+/33740/1/Documentation/soc/intel/apo... PS1, Line 50: mode if LBP2 is missing.
LBP2 is also supposed to contain the effective OBB in this case. But it […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 12:
(2 comments)
Sorry for being unresponsive must have missed a message...
https://review.coreboot.org/c/coreboot/+/33740/7/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/ifwi.dia:
PS7:
Well, it's explained here (p. 11) https://firmware.intel. […]
Looks like an implementation detail that is not used in practice (afaics). Again, have you ever seen such a layout? I think it's confusing to the reader, and you call it "common" in the text.
https://review.coreboot.org/c/coreboot/+/33740/12/Documentation/soc/intel/ap... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/33740/12/Documentation/soc/intel/ap... PS12, Line 27: common Can't say that I have seen many IFWIs, but I wouldn't call it common if it's unusual to have a BPDT entry above all S-BPDT entries.
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33740?usp=email )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Felix Singer (Code Review)
-
Matt DeVillier (Code Review)
-
Nico Huber (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)
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Stefan Reinauer (Code Review)