Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
soc/tigerlake: Correct FSP log interface
BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a..043a257 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -61,7 +61,8 @@
/* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : \ + DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39167/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39167/1/src/soc/intel/tigerlake/rom... PS1, Line 64: DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : \ Avoid unnecessary line continuations
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39167
to look at the new patch set (#2).
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
soc/tigerlake: Correct FSP log interface
BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39167/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39167/1/src/soc/intel/tigerlake/rom... PS1, Line 64: DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : \
Avoid unnecessary line continuations
Ack
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39167
to look at the new patch set (#3).
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
soc/tigerlake: Correct FSP log interface
Set DEBUG_INTERFACE_TRACEHUB as feafult and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/3
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 3: Code-Review+1
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 3: Code-Review+1
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39167/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39167/3//COMMIT_MSG@9 PS3, Line 9: feafult default
Hello Srinidhi N Kaushik, Patrick Rudolph, Meera Ravindranath, Subrata Banik, Ronak Kanabar, Aamir Bohra, Maulik V Vaghela, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39167
to look at the new patch set (#4).
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
soc/tigerlake: Correct FSP log interface
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/4
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39167/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39167/3//COMMIT_MSG@9 PS3, Line 9: feafult
default
Ack
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
soc/tigerlake: Correct FSP log interface
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-by: Aamir Bohra aamir.bohra@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, but someone else must approve Srinidhi N Kaushik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index d769615..f0f3b4c 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -61,7 +61,8 @@
/* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : + DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1044 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1043 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1042
Please note: This test is under development and might not be accurate at all!
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39167/5/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39167/5/src/soc/intel/tigerlake/rom... PS5, Line 64: DEBUG_INTERFACE_TRACEHUB Why is DEBUG_INTERFACE_TRACEHUB being set unconditionally? Shouldn't this be dependent on the NPK device being enabled in devicetree? Also, don't you need to set other UPDs for Tracehub enabling?