Wonkyu Kim uploaded patch set #4 to this change.

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soc/tigerlake: Correct FSP log interface

Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART.
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

BUG=None
BRANCH=None
TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67
---
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/4

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