Wonkyu Kim has uploaded this change for review.

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soc/tigerlake: Correct FSP log interface

BUG=None
BRANCH=None
TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67
---
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/1

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index ed6aa5a..043a257 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -61,7 +61,8 @@
 
 	/* UART Debug Log */
 	m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
-			DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
+			DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : \
+			DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB;
 	m_cfg->PcdIsaSerialUartBase = 0x0;
 	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
 

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