Change in coreboot[master]: soc/intel/common/fast_spi: Add extended decode window support
Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h 2 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4190253..a3ec0d7 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -7,9 +7,11 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <fast_spi_def.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <lib.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <spi_flash.h> #include <spi-generic.h>
@@ -246,6 +248,43 @@ } }
+/* Enable extended bios support + * Checks BIOS region in the flashmap, if its more than 16Mib, enables extended BIOS + * region support. + */ +static void fast_spi_enable_ext_bios(void) +{ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif + + size_t ext_bios_size; + uintptr_t ext_bios_base; + + if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) + return; + + fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size); + + /* Enable extended biod only if Size of Bios region is greater than 16MiB */ + if (ext_bios_size == 0 || ext_bios_base == 0) + return; + + /* Program EXT_BIOS_BAR1 with obtained ext_bios_base */ + pci_write_config32(dev, SPI_CFG_BAR1, ext_bios_base | PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* Program obtained ext_bios_size in SPI_BAR_CONTROL */ + pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB)); + /* Program EXT_BIOS EN */ + pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE); + + /* Confgiure DMI Source decode for Extended BIOS Region */ + dmi_enable_gpmr(ext_bios_base, ext_bios_size, SPI_DMI_DESTINATION_ID); + +} + /* * Program temporary BAR for SPI in case any of the stages before ramstage need * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI @@ -270,6 +309,9 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_0, spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
+ /* Enable extended bios support */ + fast_spi_enable_ext_bios(); + /* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index bafe131..0dd4ca6 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -8,6 +8,9 @@ #define SPIDVID_OFFSET 0x0 #define SPIBAR_BIOS_CONTROL 0xdc
+/* Extended Bios Support Registers */ +#define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */ + /* Bit definitions for BIOS_CONTROL */ #define SPIBAR_BIOS_CONTROL_WPD (1 << 0) #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1) @@ -15,6 +18,8 @@ #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) #define SPIBAR_BIOS_CONTROL_EISS (1 << 5) #define SPIBAR_BIOS_CONTROL_BILD (1 << 7) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE BIT(27) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff))
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 12: #define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */ please, no space before tabs
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 251: /* Coreboot coding style requires: /* * Enable extended ... * ... * ... */
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 278: Program obtained ext_bios_size in SPI_BAR_CONTROL Comment needs update. We will have to explain why 16 * MiB is being programmed here.
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 284: dmi_enable_gpmr Since GPMR programming can fail, I am thinking that we should do that first and if the return value is success only then configure EXT_BIOS_BAR1 and decode enable, etc. What do you think?
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 251: /*
Coreboot coding style requires: […]
Ack
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 278: Program obtained ext_bios_size in SPI_BAR_CONTROL
Comment needs update. We will have to explain why 16 * MiB is being programmed here.
Ack
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 284: dmi_enable_gpmr
Since GPMR programming can fail, I am thinking that we should do that first and if the return value […]
Agree, I will restructure this.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47990
to look at the new patch set (#2).
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h 2 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... PS2, Line 283: /* * please, no space before tabs
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 251: /*
Ack
done
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 278: Program obtained ext_bios_size in SPI_BAR_CONTROL
Ack
done
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 284: dmi_enable_gpmr
Agree, I will restructure this.
Done
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/47990/1/src/soc/intel/common/block/... PS1, Line 12: #define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */
please, no space before tabs
done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... PS2, Line 277: SPI_DMI_DESTINATION_ID Looks like the compiler is complaining about this being not defined for any boards other than the TGL ones. Ugh..
What do you think about: 1. Add a function soc_get_spi_dmi_destination_id() 2. Implement this for TGL and return the appropriate value (I think this will also be helpful to handle different PCH for same SoC having different destination ID).
Then, the compiler shouldn't complain.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... PS2, Line 277: SPI_DMI_DESTINATION_ID
Looks like the compiler is complaining about this being not defined for any boards other than the TG […]
sure, sounds good. Let me give it a try
Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47990
to look at the new patch set (#3).
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 64 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47990/3/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/3/src/soc/intel/common/block/... PS3, Line 277: if (dmi_enable_gpmr(ext_bios_base, ext_bios_size, soc_get_spi_dmi_destination_id()) == CB_ERR) line over 96 characters
https://review.coreboot.org/c/coreboot/+/47990/3/src/soc/intel/common/block/... PS3, Line 283: /* * please, no space before tabs
Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47990
to look at the new patch set (#4).
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 65 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 277: if (dmi_enable_gpmr(ext_bios_base, ext_bios_size, trailing whitespace
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 14: #include <soc/pcr_ids.h> Not required any more. This file doesn't use the SPI DMI macro directly. That will fix the compilation error you are seeing.
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 272: biod nit: BIOS
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 272: S nit: lowercase s
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/fast_spi.h:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 82: /* : * SOC function to get SPI-DMI Destination Id : */ Since this is a single line comment, /* SoC function to get SPI-DMI Destination Id */
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 21: BIT(27) (1 << 27) just to keep it consistent with other definitions here.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 327: fast_spi_enable_ext_bios This will have to be done outside of MMIO space enabling. Reason is because fast_spi_enable_ext_bios() calls fast_spi_get_ext_bios_window() to get base and size of BIOS region. For that, MMIO space needs to be enabled. So, the flow will have to be:
void fast_spi_early_init(uintptr_t spi_base_address) { ... /* Program Temporary BAR for SPI */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
/* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Initialize SPI to allow BIOS to write/erase on flash. */ fast_spi_init();
/* Enable extended bios support */ fast_spi_enable_ext_bios(); }
and
static void fast_spi_enable_ext_bios(void) { ...
fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size); ...
pcireg = pci_read_config16(dev, PCI_COMMAND); pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); pci_write_config16(dev, PCI_COMMAND, pcireg);
/* Perform GPMR, BAR1 and other configuration */ ...
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 327: fast_spi_enable_ext_bios
This will have to be done outside of MMIO space enabling. […]
Actually, GPMR will be programmed before disabling PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY so that if GPMR programming fails, we don't have to touch any fast spi configs at all.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47990
to look at the new patch set (#5).
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 73 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/5
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 14: #include <soc/pcr_ids.h>
Not required any more. This file doesn't use the SPI DMI macro directly. […]
Done
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 272: biod
nit: BIOS
Done
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 327: fast_spi_enable_ext_bios
Actually, GPMR will be programmed before disabling PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY so that i […]
Should we change the document to reflect this ?
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 21: BIT(27)
(1 << 27) just to keep it consistent with other definitions here.
Done
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/fast_spi.h:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 82: /* : * SOC function to get SPI-DMI Destination Id : */
Since this is a single line comment, […]
I tried to keep it consistent with other single line comments in this file For example Line 69, 73 etc. I can change it to single line if you still want me to.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47990
to look at the new patch set (#6).
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 73 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/6
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/2/src/soc/intel/common/block/... PS2, Line 277: SPI_DMI_DESTINATION_ID
sure, sounds good. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 7: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 327: fast_spi_enable_ext_bios
Should we change the document to reflect this ?
Yes, I will update the document.
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/fast_spi.h:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 82: /* : * SOC function to get SPI-DMI Destination Id : */
I tried to keep it consistent with other single line comments in this file […]
Ack.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/8/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/8/src/soc/intel/common/block/... PS8, Line 269: fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size); : : /* Enable extended BIOS only if size of Bios region is greater than 16MiB */ : if (ext_bios_size == 0 || ext_bios_base == 0) : return; Actually, we will have to unconditionally configure the window here using the base provided by the SoC. This window base has to be a multiple of 32MiB and the size is fixed too. Even though the mmap boot device might decide to use a smaller portion of the window, the decoding can only be enabled for the entire window. I will push an update to this CL and also update the documentation.
Furquan Shaikh has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Removed Code-Review+2 by Furquan Shaikh furquan@google.com
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 8:
I will wait for earlier patches to land before pushing an update to this.
Furquan Shaikh has uploaded a new patch set (#9) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 68 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/9
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/8/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/8/src/soc/intel/common/block/... PS8, Line 269: fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size); : : /* Enable extended BIOS only if size of Bios region is greater than 16MiB */ : if (ext_bios_size == 0 || ext_bios_base == 0) : return;
Actually, we will have to unconditionally configure the window here using the base provided by the S […]
Done
Furquan Shaikh has uploaded a new patch set (#10) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 68 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/10
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... PS10, Line 265: #if CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW) : /* : * Ensure that the base for the extended window in host space is a multiple of 32*MiB : * and size is fixed at 32*MiB. : */ : _Static_assert(ALIGN_UP(CONFIG_EXT_BIOS_WIN_BASE, 32 * MiB) == CONFIG_EXT_BIOS_WIN_BASE, : "Extended BIOS window base must be a multiple of 32 * MiB!"); : _Static_assert(CONFIG_EXT_BIOS_WIN_SIZE == (32 * MiB), : "Only 32MiB windows are supported for extended BIOS!"); : #endif I have intentionally added these here because currently this configuration is based on how TGL defines this. I am not sure if future platforms would have the exact same requirement. I have these in here just to catch any assumptions we might break. If it feels too much, I can drop it.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... PS10, Line 265: #if CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW) : /* : * Ensure that the base for the extended window in host space is a multiple of 32*MiB : * and size is fixed at 32*MiB. : */ : _Static_assert(ALIGN_UP(CONFIG_EXT_BIOS_WIN_BASE, 32 * MiB) == CONFIG_EXT_BIOS_WIN_BASE, : "Extended BIOS window base must be a multiple of 32 * MiB!"); : _Static_assert(CONFIG_EXT_BIOS_WIN_SIZE == (32 * MiB), : "Only 32MiB windows are supported for extended BIOS!"); : #endif
I have intentionally added these here because currently this configuration is based on how TGL defin […]
I think it is good, if this does change there may be other assumptions that need checked.
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... PS10, Line 282: pci_write_config32(dev, SPI_CFG_BAR1, CONFIG_EXT_BIOS_WIN_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY); wrap this?
Furquan Shaikh has uploaded a new patch set (#11) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/11
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... PS10, Line 265: #if CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW) : /* : * Ensure that the base for the extended window in host space is a multiple of 32*MiB : * and size is fixed at 32*MiB. : */ : _Static_assert(ALIGN_UP(CONFIG_EXT_BIOS_WIN_BASE, 32 * MiB) == CONFIG_EXT_BIOS_WIN_BASE, : "Extended BIOS window base must be a multiple of 32 * MiB!"); : _Static_assert(CONFIG_EXT_BIOS_WIN_SIZE == (32 * MiB), : "Only 32MiB windows are supported for extended BIOS!"); : #endif
I think it is good, if this does change there may be other assumptions that need checked.
Sounds good. I will keep it.
https://review.coreboot.org/c/coreboot/+/47990/10/src/soc/intel/common/block... PS10, Line 282: pci_write_config32(dev, SPI_CFG_BAR1, CONFIG_EXT_BIOS_WIN_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);
wrap this?
Done
Furquan Shaikh has uploaded a new patch set (#12) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 73 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/12
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 12: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init().
Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47990 Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 73 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4190253..24c667b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -7,6 +7,7 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <fast_spi_def.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <lib.h> #include <soc/pci_devs.h> @@ -247,6 +248,63 @@ }
/* + * Enable extended BIOS support + * Checks BIOS region in the flashmap, if its more than 16Mib, enables extended BIOS + * region support. + */ +static void fast_spi_enable_ext_bios(void) +{ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif + if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) + return; + +#if CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW) + /* + * Ensure that the base for the extended window in host space is a multiple of 32 MiB + * and size is fixed at 32 MiB. Controller assumes that the extended window has a fixed + * size of 32 MiB even if the actual BIOS region is smaller. The mapping of the BIOS + * region happens at the top of the extended window in this case. + */ + _Static_assert(ALIGN_UP(CONFIG_EXT_BIOS_WIN_BASE, 32 * MiB) == CONFIG_EXT_BIOS_WIN_BASE, + "Extended BIOS window base must be a multiple of 32 * MiB!"); + _Static_assert(CONFIG_EXT_BIOS_WIN_SIZE == (32 * MiB), + "Only 32MiB windows are supported for extended BIOS!"); +#endif + + /* Confgiure DMI Source decode for Extended BIOS Region */ + if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, + soc_get_spi_dmi_destination_id()) == CB_ERR) + return; + + /* Program EXT_BIOS_BAR1 with obtained ext_bios_base */ + pci_write_config32(dev, SPI_CFG_BAR1, + CONFIG_EXT_BIOS_WIN_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* + * Since the top 16MiB of the BIOS region is always decoded by the standard window + * below the 4G boundary, we need to map the rest of the BIOS region that lies + * below the top 16MiB in the extended window. Thus, EXT_BIOS_LIMIT will be set to + * 16MiB. This determines the maximum address in the SPI flash space that is mapped + * to the top of the extended window in the host address space. EXT_BIOS_LIMIT is + * basically the offset from the end of the BIOS region that will be mapped to the top + * of the extended window. + * This enables the decoding as follows: + -Standard decode window: (bios_region_top - 16MiB) to bios_region_top + -Extended decode window: + (bios_region_top - 16MiB - MIN(extended_window_size, bios_size - 16MiB)) + to (bios_region_top - 16MiB). + */ + pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB)); + + /* Program EXT_BIOS EN */ + pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE); +} + +/* * Program temporary BAR for SPI in case any of the stages before ramstage need * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI * enumeration. @@ -270,6 +328,12 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_0, spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
+ /* + * Enable extended bios support. Since it configures memory BAR, this is done before + * enabling MMIO space. + */ + fast_spi_enable_ext_bios(); + /* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index bafe131..883c3ce 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -8,6 +8,9 @@ #define SPIDVID_OFFSET 0x0 #define SPIBAR_BIOS_CONTROL 0xdc
+/* Extended Bios Support Registers */ +#define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */ + /* Bit definitions for BIOS_CONTROL */ #define SPIBAR_BIOS_CONTROL_WPD (1 << 0) #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1) @@ -15,6 +18,8 @@ #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) #define SPIBAR_BIOS_CONTROL_EISS (1 << 5) #define SPIBAR_BIOS_CONTROL_BILD (1 << 7) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff))
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 0a7e64d..81437b6 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -73,12 +73,15 @@ * Enable SPI Write protect. */ void fast_spi_enable_wp(void); - /* * Get base and size of extended BIOS decode window used at runtime in host address space. If * the BIOS region is not greater than 16MiB, then this function returns 0 for both base and * size. */ void fast_spi_get_ext_bios_window(uintptr_t *base, size_t *size); +/* + * SOC function to get SPI-DMI Destination Id + */ +uint32_t soc_get_spi_dmi_destination_id(void);
#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */
-
build bot (Jenkins) (Code Review) -
Duncan Laurie (Code Review)
-
Furquan Shaikh (Code Review)
-
Srinidhi N Kaushik (Code Review)