Srinidhi N Kaushik has uploaded this change for review.
soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS
region decode window. This configuration needs to be performed
as early as possible in the boot flow. This is required to
ensure that any access to the SPI flash region below 16MiB in
coreboot is decoded correctly. The configuration for the extended
BIOS window if required is done as part of fast_spi_early_init().
Changes include:
1. Make a call to fast_spi_enable_ext_bios() before the bus master
and memory space is enabled for the fast SPI controller.
2. Added a helper function fast_spi_enable_ext_bios() which calls
fast_spi_get_ext_bios_window() to get details about the extended
BIOS window from the boot media map.
3. Depending upon the SPI flash device used by the mainboard and
the size of the BIOS region in the flashmap, this function will
have to perform this additional configuration only if the BIOS
region is greater than 16MiB
4. Adddditionally, set up the general purpose memory range
registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
2 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 4190253..a3ec0d7 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -7,9 +7,11 @@
#include <commonlib/helpers.h>
#include <cpu/x86/mtrr.h>
#include <fast_spi_def.h>
+#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <lib.h>
#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
#include <spi_flash.h>
#include <spi-generic.h>
@@ -246,6 +248,43 @@
}
}
+/* Enable extended bios support
+ * Checks BIOS region in the flashmap, if its more than 16Mib, enables extended BIOS
+ * region support.
+ */
+static void fast_spi_enable_ext_bios(void)
+{
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
+
+ size_t ext_bios_size;
+ uintptr_t ext_bios_base;
+
+ if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
+ return;
+
+ fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size);
+
+ /* Enable extended biod only if Size of Bios region is greater than 16MiB */
+ if (ext_bios_size == 0 || ext_bios_base == 0)
+ return;
+
+ /* Program EXT_BIOS_BAR1 with obtained ext_bios_base */
+ pci_write_config32(dev, SPI_CFG_BAR1, ext_bios_base | PCI_BASE_ADDRESS_SPACE_MEMORY);
+
+ /* Program obtained ext_bios_size in SPI_BAR_CONTROL */
+ pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB));
+ /* Program EXT_BIOS EN */
+ pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE);
+
+ /* Confgiure DMI Source decode for Extended BIOS Region */
+ dmi_enable_gpmr(ext_bios_base, ext_bios_size, SPI_DMI_DESTINATION_ID);
+
+}
+
/*
* Program temporary BAR for SPI in case any of the stages before ramstage need
* to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI
@@ -270,6 +309,9 @@
pci_write_config32(dev, PCI_BASE_ADDRESS_0,
spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
+ /* Enable extended bios support */
+ fast_spi_enable_ext_bios();
+
/* Enable Bus Master and MMIO Space */
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index bafe131..0dd4ca6 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -8,6 +8,9 @@
#define SPIDVID_OFFSET 0x0
#define SPIBAR_BIOS_CONTROL 0xdc
+/* Extended Bios Support Registers */
+#define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */
+
/* Bit definitions for BIOS_CONTROL */
#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
#define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1)
@@ -15,6 +18,8 @@
#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
#define SPIBAR_BIOS_CONTROL_BILD (1 << 7)
+#define SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE BIT(27)
+#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff))
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
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