Kevin Cody-Little has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37995 )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I (and eventually P10S-M) Kaby Lake server boards. This is still very broken but boots to a serial console, and one of the onboard network ports works, so long as a known good kernel is used as the payload.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc A src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c A src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd 26 files changed, 1,452 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/1
diff --git a/src/mainboard/asus/p10s-series/Kconfig b/src/mainboard/asus/p10s-series/Kconfig new file mode 100644 index 0000000..eac2272 --- /dev/null +++ b/src/mainboard/asus/p10s-series/Kconfig @@ -0,0 +1,89 @@ +config BOARD_ASUS_P10S_SERIES + def_bool n + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_HAS_LPC_TPM + select DRIVERS_ASPEED_AST2050 + select SUPERIO_ASPEED_AST2400 + select GENERATE_SMBIOS_TABLES + select IPMI_KCS + select MAINBOARD_NO_FSP_GOP + select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND + select NO_FADT_8042 + +if BOARD_ASUS_P10S_SERIES + +config MAINBOARD_FAMILY + string + default "ASUS_P10S_SERIES" + +config MAINBOARD_PART_NUMBER + string + default "P10S-I" if BOARD_ASUS_P10S_I + default "P10S-M" if BOARD_ASUS_P10S_M + +config MAINBOARD_DIR + string + default "asus/p10s-series" + +config VARIANT_DIR + string + default "p10s-i" if BOARD_ASUS_P10S_I + default "p10s-m" if BOARD_ASUS_P10S_M + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +if VBOOT + +config VBOOT_SLOTS_RW_AB + default y + +endif + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB + +config CBFS_SIZE + hex + default 0xb00000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config CONSOLE_POST + bool + default y + +config POST_DEVICE + bool + default n + +config DIMM_SPD_SIZE + int + default 512 + +endif # BOARD_ASUS_P10S_SERIES diff --git a/src/mainboard/asus/p10s-series/Kconfig.name b/src/mainboard/asus/p10s-series/Kconfig.name new file mode 100644 index 0000000..bd696e9 --- /dev/null +++ b/src/mainboard/asus/p10s-series/Kconfig.name @@ -0,0 +1,7 @@ +config BOARD_ASUS_P10S_I + bool "P10S-I" + select BOARD_ASUS_P10S_SERIES + +#config BOARD_ASUS_P10S_M +# bool "P10S-M" +# select BOARD_ASUS_P10S_SERIES diff --git a/src/mainboard/asus/p10s-series/Makefile.inc b/src/mainboard/asus/p10s-series/Makefile.inc new file mode 100644 index 0000000..cab662a --- /dev/null +++ b/src/mainboard/asus/p10s-series/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/asus/p10s-series/acpi/ec.asl b/src/mainboard/asus/p10s-series/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/ec.asl diff --git a/src/mainboard/asus/p10s-series/acpi/mainboard.asl b/src/mainboard/asus/p10s-series/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/mainboard.asl diff --git a/src/mainboard/asus/p10s-series/acpi/superio.asl b/src/mainboard/asus/p10s-series/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/superio.asl diff --git a/src/mainboard/asus/p10s-series/acpi_tables.c b/src/mainboard/asus/p10s-series/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi_tables.c diff --git a/src/mainboard/asus/p10s-series/board_info.txt b/src/mainboard/asus/p10s-series/board_info.txt new file mode 100644 index 0000000..cfa02bc --- /dev/null +++ b/src/mainboard/asus/p10s-series/board_info.txt @@ -0,0 +1,2 @@ +Category: server +Vendor name: ASUS diff --git a/src/mainboard/asus/p10s-series/bootblock.c b/src/mainboard/asus/p10s-series/bootblock.c new file mode 100644 index 0000000..75afd2e --- /dev/null +++ b/src/mainboard/asus/p10s-series/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <delay.h> +#include <console/uart.h> + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_gpio(); + early_config_superio(); +} diff --git a/src/mainboard/asus/p10s-series/cmos.default b/src/mainboard/asus/p10s-series/cmos.default new file mode 100644 index 0000000..d564953 --- /dev/null +++ b/src/mainboard/asus/p10s-series/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable diff --git a/src/mainboard/asus/p10s-series/cmos.layout b/src/mainboard/asus/p10s-series/cmos.layout new file mode 100644 index 0000000..03aea17 --- /dev/null +++ b/src/mainboard/asus/p10s-series/cmos.layout @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +# ----------------------------------------------------------------- +# coreboot config options: bootloader +448 128 r 0 vbnv + +# ----------------------------------------------------------------- +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/p10s-series/devicetree.cb b/src/mainboard/asus/p10s-series/devicetree.cb new file mode 100644 index 0000000..efb1585 --- /dev/null +++ b/src/mainboard/asus/p10s-series/devicetree.cb @@ -0,0 +1,174 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Disabled" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # SATA configuration + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "SataPortsDevSlp" = "{\ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # superspeed_inter-chip_supplement (SSIC) disabled + register "SsicPortEnable" = "0" + + # USB + register "usb2_ports" = "{ + [0] = USB2_PORT_EMPTY, + [1] = USB2_PORT_EMPTY, + [2] = USB2_PORT_EMPTY, + [3] = USB2_PORT_EMPTY, + [4] = USB2_PORT_EMPTY, + [5] = USB2_PORT_EMPTY, + [6] = USB2_PORT_EMPTY, + [7] = USB2_PORT_EMPTY, + [8] = USB2_PORT_EMPTY, + [9] = USB2_PORT_EMPTY, + [10] = USB2_PORT_EMPTY, + [11] = USB2_PORT_EMPTY, + [12] = USB2_PORT_EMPTY, + [13] = USB2_PORT_EMPTY, + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_EMPTY, + [1] = USB3_PORT_EMPTY, + [2] = USB3_PORT_EMPTY, + [3] = USB3_PORT_EMPTY, + [4] = USB3_PORT_EMPTY, + [5] = USB3_PORT_EMPTY, + [6] = USB3_PORT_EMPTY, + [7] = USB3_PORT_EMPTY, + [8] = USB3_PORT_EMPTY, + [9] = USB3_PORT_EMPTY, + }" + + # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "s0ix_enable" = "1" + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + + # No extra VR mailbox command + register "SendVrMbxCmd" = "0" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # CPU PCIe Port 10 (x16) + device pci 01.1 off end # CPU PCIe Port 11 (x8) + device pci 01.2 off end # CPU PCIe Port 12 (x4) + device pci 02.0 off end # Integrated Graphics Device (IGD) + device pci 04.0 off end # SA thermal subsystem + device pci 05.0 off end # Imaging Unit + device pci 08.0 off end # Gaussion Mixture Model (GMM) + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1b.0 off end # PCH PCIe Port 17 + device pci 1b.1 off end # PCH PCIe Port 18 + device pci 1b.2 off end # PCH PCIe Port 19 + device pci 1b.3 off end # PCH PCIe Port 20 + device pci 1c.0 on end # PCH PCIe Port 1 + device pci 1c.1 off end # PCH PCIe Port 2 + device pci 1c.2 off end # PCH PCIe Port 3 + device pci 1c.3 off end # PCH PCIe Port 4 + device pci 1c.4 off end # PCH PCIe Port 5 + device pci 1c.5 on end # PCH PCIe Port 6 + device pci 1c.6 on end # PCH PCIe Port 7 + device pci 1c.7 off end # PCH PCIe Port 8 + device pci 1d.0 off end # PCH PCIe Port 9 + device pci 1d.1 off end # PCH PCIe Port 10 + device pci 1d.2 off end # PCH PCIe Port 11 + device pci 1d.3 off end # PCH PCIe Port 12 + device pci 1d.4 off end # PCH PCIe Port 13 + device pci 1d.5 off end # PCH PCIe Port 14 + device pci 1d.6 off end # PCH PCIe Port 15 + device pci 1d.7 off end # PCH PCIe Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # SPI #0 + device pci 1f.0 on # LPC Interface + chip superio/common + device pnp 2e.0 on end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # SPI Controller + device pci 1f.6 off end # GbE + device pci 1f.7 off end # Intel Trace Hub + end +end diff --git a/src/mainboard/asus/p10s-series/dsdt.asl b/src/mainboard/asus/p10s-series/dsdt.asl new file mode 100644 index 0000000..b88b1d2 --- /dev/null +++ b/src/mainboard/asus/p10s-series/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/p10s-series/include/mainboard.h b/src/mainboard/asus/p10s-series/include/mainboard.h new file mode 100644 index 0000000..ce84441 --- /dev/null +++ b/src/mainboard/asus/p10s-series/include/mainboard.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _BOARD_ASUS_P10S_SERIES_H +#define _BOARD_ASUS_P10S_SERIES_H + +#include <device/device.h> + +void variant_mainboard_init(struct device *dev); + +#endif /* _OARD_ASUS_P10S_SERIES_H */ diff --git a/src/mainboard/asus/p10s-series/mainboard.c b/src/mainboard/asus/p10s-series/mainboard.c new file mode 100644 index 0000000..750c856 --- /dev/null +++ b/src/mainboard/asus/p10s-series/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard.h> +#include <device/device.h> + +__weak void variant_mainboard_init(struct device *dev) +{ +} + +static void mainboard_init(struct device *dev) +{ + /* do common init */ + // placeholder for common mainboard initialization + + /* do variant init */ + variant_mainboard_init(dev); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/p10s-series/ramstage.c b/src/mainboard/asus/p10s-series/ramstage.c new file mode 100644 index 0000000..a16678e --- /dev/null +++ b/src/mainboard/asus/p10s-series/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asus/p10s-series/romstage.c b/src/mainboard/asus/p10s-series/romstage.c new file mode 100644 index 0000000..cb1f105 --- /dev/null +++ b/src/mainboard/asus/p10s-series/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_SERVER; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt b/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt new file mode 100644 index 0000000..adfd6c0 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: ASUS +Board name: P10S-I +Board URL: https://www.asus.com/us/Commercial-Servers-Workstations/P10S-I/ +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h b/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h new file mode 100644 index 0000000..a08ea53 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_ASUS_P10S_I_H +#define _GPIO_ASUS_P10S_I_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { +/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), +/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), +/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), +/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), +/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), +/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), +/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), +/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), +/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), +/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), +/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), +/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), +/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), +/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), +/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), +/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), +/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), +/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), +/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), +/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), +/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), +/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), +/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), +/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), +/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), +/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), +/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), +/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), +/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), +/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), +/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), +/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), +/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), +/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), +/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), +/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), +/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), +/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), +/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), +/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), +/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), +/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), +/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), +/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), +/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), +/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), +}; + + +/*** XXX TODO XXX */ +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* LPC */ + +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +}; + +#endif /* _GPIO_ASUS_P10S_I_H */ diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb b/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb new file mode 100644 index 0000000..2e722e4 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb @@ -0,0 +1,143 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration +# # Enable JPCIE1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + +# # Enable ASpeed PCI bridge +# register "PcieRpEnable[2]" = "1" +# register "PcieRpClkReqSupport[2]" = "0" + +# # Enable X550T (10GbE) +# register "PcieRpEnable[4]" = "1" +# register "PcieRpClkReqSupport[4]" = "0" + + # Enable I210 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "0" + + # Enable I210 + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "0" + + # Enable M.2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on # CPU PCIe Slot + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X16" "SlotDataBusWidth16X" + end + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1c.5 on # PCI Express Port 5 + device pci 00.0 on end # 1GbE + end + device pci 1c.6 on # PCI Express Port 6 + device pci 00.0 on end # 1GbE + end + device pci 1d.0 on # PCI Express Port 9 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2242" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc b/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt b/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt new file mode 100644 index 0000000..b868459 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: ASUS +Board name: P10S-M +Board URL: https://www.asus.com/us/Commercial-Servers-Workstations/P10S-M/ +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h b/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h new file mode 100644 index 0000000..4c551d1 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_ASUS_P10S_M_H +#define _GPIO_ASUS_P10S_M_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */ + _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */ + _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_B */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */ + + /* GPIO Group GPP_C */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */ + //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */ + //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */ + //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */ + _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_D */ + _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0x04000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_E */ + _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */ + + /* GPIO Group GPP_F */ + _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */ + _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */ + _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_G */ + _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */ + _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */ + _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_H */ + _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */ + _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */ + _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */ + _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */ + _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */ + _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */ + _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_I */ + _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */ + + /* GPIO Group GPD */ + _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */ + _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + /* LPC */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + + /* Serial interrupt */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ +}; + +#endif /* _GPIO_ASUS_P10S_M_H */ diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c b/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c new file mode 100644 index 0000000..7cf8883 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard.h> +#include <device/device.h> +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +void variant_mainboard_init(struct device *dev) +{ + /* TODO: + * Find out why the polarities from gpio.h gets overwritten by FSP. + * This sets irq polarity to the same values as vendor + * but I do not know if this is really needed.... + */ + itss_set_irq_polarity(33, 0); + itss_set_irq_polarity(34, 0); + + // TODO: NMI; is this needed? vendor sets it + pcr_write32(0xae, 0x01e4, 0x00000004); + pcr_write32(0xae, 0x01e8, 0x00000040); +} diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb b/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb new file mode 100644 index 0000000..ea90e0b --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb @@ -0,0 +1,124 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_G" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration + register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 + register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 + register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 + register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 + register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA + + # USB configuration + # USB0/1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + + # USB2/3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + + # USB4/5 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + + # USB6/7 (USB3.0) + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8/9 (USB3.0) + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + + # USB10 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end + device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1d.0 on # PCH PCIe Port 9 + device pci 00.0 on end # GbE 1 + end + device pci 1d.1 on # PCH PCIe Port 10 + device pci 00.1 on end # GbE 2 + end + device pci 1d.2 on # PCH PCIe Port 11 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 / COM1 (ext) + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 / COM2 (int) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd b/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd new file mode 100644 index 0000000..a295680 --- /dev/null +++ b/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0xb00000 { + RW_SECTION_A@0x0 0x33e000 { + VBLOCK_A@0x0 0x20000 + FW_MAIN_A(CBFS)@0x20000 0x31dfc0 + RW_FWID_A@0x33dfc0 0x40 + } + RW_SECTION_B@0x33e000 0x33e000 { + VBLOCK_B@0x0 0x20000 + FW_MAIN_B(CBFS)@0x20000 0x31dfc0 + RW_FWID_B@0x33dfc0 0x40 + } + MISC_RW@0x67d000 0x62000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x20000 0x2000 + SMMSTORE(PRESERVE)@0x22000 0x40000 + } + WP_RO@0x6df000 0x421000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x41d000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x32d000 + } + } + } +}
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37995
to look at the new patch set (#2).
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I (and eventually P10S-M) Kaby Lake server boards. This is still very broken but boots to a serial console, and one of the onboard network ports works, so long as a known good kernel is used as the payload.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc A src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c A src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd 26 files changed, 1,452 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37995
to look at the new patch set (#3).
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I (and eventually P10S-M) Kaby Lake server boards. This is still very broken but boots to a serial console, and one of the onboard network ports works, so long as a known good kernel is used as the payload.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc A src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c A src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd 26 files changed, 1,445 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37995 )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
Patch Set 3:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37995/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37995/3//COMMIT_MSG@10 PS3, Line 10: P10S-M I would not add this board until you have boot-tested it. If you're going to get your hands on one of these soon, then it's not a problem
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 3: Enable I am not sure
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 33: // CPU I would drop this comment
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 35: : Scope (_SB) { : Device (PCI0) Device (_SB.PCI0)
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 44: // Chipset specific sleep states I just dropped these with CB:37855
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/include/mainboard.h:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 21: #endif /* _OARD_ASUS_P10S_SERIES_H */ OARD?
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h:
PS3: How did you generate this?
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h:
PS3: How did you generate this?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37995
to look at the new patch set (#4).
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I Kaby Lake server boards, and perhaps someday others of the same family. This is still very broken but boots, and one of the onboard network ports works, so long as a known good kernel is used as the payload. Sometimes the serial port works. Work continues, this push is just to make the code visible to others as early in the process as possible.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd M src/soc/intel/skylake/include/soc/usb.h 22 files changed, 1,021 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/4
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37995
to look at the new patch set (#5).
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I Kaby Lake server boards, and perhaps someday others of the same family. This is still very broken but boots, and one of the onboard network ports works, so long as a known good kernel is used as the payload. Sometimes the serial port works. Work continues, this push is just to make the code visible to others as early in the process as possible.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd M src/soc/intel/skylake/include/soc/usb.h 22 files changed, 1,021 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/5
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37995
to look at the new patch set (#6).
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I Kaby Lake server boards, and perhaps someday others of the same family. This is still very broken but boots, and one of the onboard network ports works, so long as a known good kernel is used as the payload. Serial port sems to be working now. Work continues, this push is just to make the code visible to others as early in the process as possible.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd M src/soc/intel/skylake/include/soc/usb.h 22 files changed, 1,060 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/6
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37995
to look at the new patch set (#7).
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I Kaby Lake server boards, and perhaps someday others of the same family. This is still very broken but boots, and one of the onboard network ports works, so long as a known good kernel is used as the payload. Serial port sems to be working now. Work continues, this push is just to make the code visible to others as early in the process as possible.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd M src/soc/intel/skylake/include/soc/usb.h 22 files changed, 1,059 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/7
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37995
to look at the new patch set (#8).
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
mainboard/asus/p10s-series: Initial port to ASUS P10S-I
Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I Kaby Lake server boards, and perhaps someday others of the same family. This is still somewhat broken but boots Linux, the onboard network ports work, the serial port works, so long as a known good kernel is used as the payload. Haven't gotten the vga port to work yet. Development continues, this push is just to make the code visible to others as early in the process as possible.
Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody kcodyjr@gmail.com --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd M src/soc/intel/skylake/include/soc/usb.h 22 files changed, 1,057 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/8
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37995 )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
Patch Set 8:
(4 comments)
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 33: // CPU
I would drop this comment
Done
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 35: : Scope (_SB) { : Device (PCI0)
Device (_SB. […]
Done
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 44: // Chipset specific sleep states
I just dropped these with CB:37855
Done
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/include/mainboard.h:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 21: #endif /* _OARD_ASUS_P10S_SERIES_H */
OARD?
Done
Kevin Cody has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37995 )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
Patch Set 9:
(8 comments)
Apologies, I hadn't seen that my replies were still drafts.
https://review.coreboot.org/c/coreboot/+/37995/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37995/3//COMMIT_MSG@10 PS3, Line 10: P10S-M
I would not add this board until you have boot-tested it. […]
Probably not. At the moment, I've got the key CONFIG value commented out so it won't offer it as a build target. It just seemed to make sense to maintain the variant/ setup from the Supermicro board I'm basing this on.
Okay, I've dropped the variants/p10s-m directory and changed the wording in the latest commit. For now, p10s-i only, but it's set up so maybe someday others in the same family can be done.
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 3: Enable
I am not sure
Neither am I. Sure does look like it actually disables all that.
Changed in the latest push.
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 33: // CPU
I would drop this comment
Dropped.
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 35: : Scope (_SB) { : Device (PCI0)
Device (_SB. […]
Changed thusly.
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 44: // Chipset specific sleep states
I just dropped these with CB:37855
Comment dropped.
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/include/mainboard.h:
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... PS3, Line 21: #endif /* _OARD_ASUS_P10S_SERIES_H */
OARD?
Fixed.
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h:
PS3:
How did you generate this?
I didn't. This is inherited verbatim from the Supermicro board I'm basing this on.
Replaced with values generated by a perl script I wrote that parses the output of inteltool -g and spits out the proper high-level macros. The new values still aren't quite exactly right but they're closer.
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h:
PS3:
How did you generate this?
I didn't. This is inherited verbatim from the Supermicro board I'm basing this on.
File dropped.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37995 )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
Patch Set 9: Code-Review+1
(9 comments)
https://review.coreboot.org/c/coreboot/+/37995/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37995/3//COMMIT_MSG@10 PS3, Line 10: P10S-M
Probably not. […]
Ack. Turning a regular board into a variant-enabled setup is rather easy.
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... PS9, Line 23: This is a string, it doesn't need to look like a Kconfig symbol
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... PS9, Line 28: This can be added when the respective boards are ported. Currently, it's dead code
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/bootblock.c:
PS9: Missing a few things here, check other boards to find additional things to put here
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h:
PS3:
I didn't. This is inherited verbatim from the Supermicro board I'm basing this on. […]
Would be nice if you could put this script somewhere, so that others can use it. Even if it's an ugly hack, it won't be worse than hswgpio.c on my github :D
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... PS9, Line 230: The current entries look good. Maybe also add the SMBus pads because you have to read SPDs off the DIMMs.
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt:
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... PS9, Line 30: Ǹote: these are PCIe root ports. What they are connected to depends on the mainboard. In the case of M.2, it's very likely that CLKREQ# is used.
https://review.coreboot.org/c/coreboot/+/37995/9/src/mainboard/asus/p10s-ser... PS9, Line 39: lsusb might help
https://review.coreboot.org/c/coreboot/+/37995/3/src/mainboard/asus/p10s-ser... File src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h:
PS3:
I didn't. This is inherited verbatim from the Supermicro board I'm basing this on. […]
Ack
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37995?usp=email )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
Felix Singer has restored this change. ( https://review.coreboot.org/c/coreboot/+/37995?usp=email )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
Restored
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37995?usp=email )
Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Kevin Cody (Code Review)
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Kevin Cody-Little (Code Review)
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Martin L Roth (Code Review)